Lattice Semiconductor MachXO2 - Acronyms in this Document

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MachXO2 and MachXO3 Starter Kit Evaluation Board User Guide

Evaluation Board User Guide

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-EB-02036-1.4 5

Acronyms in This Document

A list of acronyms used in this document.

Acronym

Definition

DIP

Dual In-line Package

FPGA

Field-Programmable Gate Array

LED

Light Emitting Diode

LUT

Look-Up Table

NVCM

Non Volatile Configuration Memory

PCB

Printed Circuit Board

RoHS

Restriction of Hazardous Substances Directive

USB

Universal Serial Bus

WDT

Watchdog Timer

Main Page

Table of Contents3
Acronyms in this Document5
Introduction6
Features7
Figure 2.1. Machxo3 Board (Machxo3L Version), Top Side7
Figure 2.2. Machxo3 Board (Machxo3L Version), Bottom Side8
Storage Handling9
Software Requirements10
Machxo2 and Machxo3 Devices11
Demonstration Design12
Overview12
Figure 7.1. Machxo2 and Machxo3L/Lf-6900C Block Diagram12
Run the Demonstration Design13
Figure 6.1. Demonstration Design Block Diagram13
Table 7.1. Starter Kit Components and Interfaces13
Table 6.1. DIP Switch and LED Behavior14
Download Demo Designs15
Programming a Demo Design with the Lattice Diamond Programmer15
Machxo2 and Machxo3 Starter Kits17
Subsystems17
Clock Sources17
Expansion Header Landings17
Table 7.2. Expansion Connector Reference17
Table 7.3. Expansion Header Pin Information (J3)18
Table 7.4. Expansion Header Pin Information (J4)19
Table 7.5. Expansion Header Pin Information (J6)20
Table 7.6. Expansion Header Pin Information (J8)21
Figure 7.2. J3/J4 Header Landing Callout22
Figure 7.3. J6/J8 Header Landing Callout22
Machxo2/Machxo3 FPGA23
Programming Interface Circuits23
Figure 7.4. J1 Header Landing and LED Array Callout23
Table 7.7. Machxo2 and Machxo3 FPGA Interface Reference23
Table 7.8. USB/JTAG Interface Reference23
Leds24
Power Supply24
Test Points24
USB Programming and Debug Interface24
Table 7.9. JTAG Programming Pin Information24
Table 7.10. SPI Programming Pin Information24
Table 7.11. I 2 C Programming Pin Information24
Table 7.12. Power and User Leds Reference24
Board Modifications25
Bypassing the USB Programming Interface25
Applying External Power25
Measuring Bank and Core Power25
Mechanical Specifications25
Environmental Requirements25
Table 7.13. USB Interface Reference25
Troubleshooting26
Leds Do Not Flash26
USB Cable Not Detected26
Accessing the Troubleshooting the USB Driver Installation Guide26
Restoring Original Demo Design26
Ordering Information27
Table 9.1. Ordering Information27
Technical Support Assistance28
Appendix A. Schematic Diagrams29
Figure A.1. Block Diagram29
Figure A.2. USB Interface to JTAG30
Figure A.3. FPGA31
Figure A.4. FPGA32
Figure A.5. Power Leds33
Figure A.6. Bank 2 I/O34
Figure A.7. Bank 3, 4, 5 I/O35
Figure A.8. Power Decoupling and Leds36
Appendix B. Bill of Materials37
Revision History39

Lattice Semiconductor MachXO2 - Acronyms in this Document

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