Lattice Semiconductor MachXO2 - Appendix A. Schematic Diagrams

MachXO2 Programming and Configuration Usage Guide
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TransFR Operation
The MachXO2, like other Lattice FPGAs, provides for the TransFR™ capability. TransFR is described in TN1087
Minimizing System Interruption During Configuration Using TransFR Technology. The following is an example of
how you can update bitstream in MachXO2 by using the TransFR feature.
Figure 15. Bitstream Update Using TransFR
The example assumes that you have the golden image stored in Flash in order to initiate the system, and will then
use SPI PROM as a resource for image updates without disturbing the system. Figure 16 shows the process flow
for performing this task.
Figure 16. Example Process Flow
SPI PROM
with New
Image
sys clock
MachXO2
System Board
Global Reset
Configuration
SRAM
Flash with
Golden Image
S
y
stem r
unnin
g
Program SPI PROM
with new pattern
1
Halt sys clk
Issue TransFR Refresh
instruction through JTAG
3
System running again
with new image
4
Release s
y
s clock
Global Reset
occurs
Program MachXO2 Feature
Row to Dual-Boot through
JTAG
2, 5
Assume MachXO2
Flash has been
programmed and
running
Can use
Diamond Programmer
Notes:
1. User can use operations such as “SPI Flash Background Erase, Program, Verify” for this.
2. User can use operations such as “XFlash Program Feature Rows” for this.
3. User can use operations like “XFlash TransFR” for this.
4. If new image failed to cong MachXO2, the golden image in Flash will still cong MachXO2,
so system will still be running with original image.
5. Feature Row only needs to be programmed if changes need to be made, for instance,
disable or enable JTAG, Slave Port. If no changes need to be made, please skip this step.
6. This step is optional.
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