www.latticesemi.com/dynamic/view_document.cfm?document_id=46300
www.latticesemi.com/dynamic/view_document.cfm?document_id=46300
www.latticesemi.com/dynamic/view_document.cfm?document_id=46300
Refresh was successful if Status Register BUSY bit = 0, DONE bit = 1,
and Configuration Check Status bits = 000. See TN1246, Using User
Flash Memory and Hardened Control Functions in MachXO2 Devices
Reference Guide for complete Read Status Register command details.
Transmit Refresh
Command (0x79)
No
No
Ye s
Ye s
Ye s
Offline
Mode?
Transmit Disable
Configuration
Interface Command
(0x26)
Wait t
REFRESH
Done
Check
for
Success?
Clean Up
Exit
Transmit
Read Status
Register Command
(0x3C)
Ye s
No
No
Refresh
Successful?
Retry
Count
Exceeded?
6
Refresh?
Ye s
To 'Read Status Register' over the I
2
C configuration port,
the MachXO2 must have the EFB instantiated and with the
EFB 'wb_clk_i' input connected to a valid clock source
of at least 7.5x the I2C bus rate. If the EFB is not instantiated
(not recommended), the I
2
C configuration port 'Read Status Register'
readback data will be 0xFFFF. To temporarily work around this limitation,
the 'Transmit Read Status Register' step can be omitted.
Notes:
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