LTC6804-1/LTC6804-2
21
680412fc
For more information www.linear.com/LTC6804-1
operaTion
isoSPI STATE DESCRIPTIONS
Note: The LTC6804-1 has two isoSPI ports (A and B), for
daisy-chain communication. The LTC6804-2 has only one
isoSPI port (A), for parallel-addressable communication.
IDLE State
The isoSPI ports are powered down.
When isoSPI port A receives a WAKEUP signal (see Wak-
ing Up the Serial Interface), the isoSPI enters the READY
state. This transition happens quickly (within t
READY
) if
the Core is in the STANDBY state because the DRIVE and
V
REG
pins are already biased up. If the Core is in the SLEEP
state when the isoSPI receives a WAKEUP signal, then it
transitions to the READY state within t
WAKE
.
READY State
The isoSPI port(s) are ready for communication. Port
B is enabled only for LTC6804-1, and is not present on
the LTC6804-2. The serial interface current in this state
depends on if the part is LTC6804-1 or LTC6804-2, the
status of the ISOMD pin, and R
BIAS
= R
B1
+ R
B2
(the
external resistors tied to the IBIAS pin).
If there is no activity (i.e., no WAKEUP signal) on port A
for greater than t
IDLE
= 5.5ms, the LTC6804 goes to the
IDLE state. When the serial interface is transmitting or
receiving data the LTC6804 goes to the ACTIVE state.
ACTIVE State
The LTC6804 is transmitting/receiving data using one or
both of the isoSPI ports. The serial interface consumes
maximum power in this state. The supply current increases
with clock frequency as the density of isoSPI pulses
increases.
POWER CONSUMPTION
The LTC6804 is powered via two pins: V
+
and V
REG
. The
V
+
input requires voltage greater than or equal to the top
cell voltage, and it provides power to the high voltage
elements of the core circuitry. The V
REG
input requires
5V and provides power to the remaining core circuitry
and the isoSPI circuitry. The V
REG
input can be powered
through an external transistor, driven by the regulated
DRIVE output pin. Alternatively, V
REG
can be powered by
an external supply.
The power consumption varies according to the opera-
tional states. Table 1 and Table 2 provide equations to
approximate the supply pin currents in each state. The V
+
pin current depends only on the Core state and not on the
isoSPI state. However, the V
REG
pin current depends on
both the Core state and isoSPI state, and can therefore be
divided into two components. The isoSPI interface draws
current only from the V
REG
pin.
I
REG
= I
REG(CORE)
+ I
REG(isoSPI)
Table 1. Core Supply Current
STATE I
V
+ I
REG(CORE)
SLEEP
V
REG
= 0V 3.8µA 0µA
V
REG
= 5V 1.6µA 2.2µA
STANDBY 32µA 35µA
REFUP 550µA 450µA
MEASURE 550µA 11.5mA
In the SLEEP state the V
REG
pin will draw approximately
2.2µA if powered by a external supply. Otherwise, the V
+
pin will supply the necessary current.
ADC OPERATION
There are two ADCs inside the LTC6804. The two ADCs
operate simultaneously when measuring twelve cells. Only
one ADC is used to measure the general purpose inputs.
The following discussion uses the term ADC to refer to
one or both ADCs, depending on the operation being
performed. The following discussion will refer to ADC1
and ADC2 when it is necessary to distinguish between the
two circuits, in timing diagrams, for example.
ADC Modes
The ADCOPT bit (CFGR0[0]) in the configuration register
group and the mode selection bits MD[1:0] in the conver-
sion command together provide 6 modes of operation for
the ADC which correspond to different over sampling ratios
(OSR). The accuracy of these modes are summarized in
Table 3. In each mode, the ADC first measures the inputs,
and then performs a calibration of each channel. The
names of the modes are based on the –3dB bandwidth
of the ADC measurement.
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