LTC6804-1/LTC6804-2
54
680412fc
For more information www.linear.com/LTC6804-1
operaTion
NAME DESCRIPTION VALUES
MUXFAIL Multiplexer Self-
Test Result
Read: 0 -> Multiplexer Passed Self Test 1 -> Multiplexer Failed Self Test
THSD Thermal
Shutdown Status
Read: 0 -> Thermal Shutdown Has Not Occurred 1 -> Thermal Shutdown Has Occurred
THSD Bit Cleared to 0 on Read of Status RegIster Group B
ICOMn Initial
Communication
Control Bits
Write I2C 0110 0001 0000 0111
STAR
T STOP BLANK NO TRANSMIT
SPI 1000 1001 1111
CSB Low CSB High NO TRANSMIT
Read I2C 0110 0001 0000 0111
START from Master STOP from Master SDA Low Between Bytes SDA High Between
Bytes
SPI 0111
Dn I
2
C/SPI
Communication
Data Byte
Data Transmitted (Received) to (From) I
2
C/SPI Slave Device
FCOMn Final
Communication
Control Bits
Write I2C 0000 1000 1001
Master ACK Master NACK Master NACK + STOP
SPI X000 1001
CSB Low CSB High
Read I2C 0000 0111 1111 0001 1001
ACK from Master ACK from Slave NACK from Slave ACK from Slave +
STOP from Master
NACK from Slave
+ STOP from
Master
SPI 1111
*Voltage equations use the decimal value of registers, 0 to 4095 for 12 bits and 0 to 65535 for 16 bits.
PROGRAMMING EXAMPLES
The following examples use a configuration of 3 stacked
LTC6804-1 devices: S1, S2, S3. Port A on device S1 is
configured in SPI mode (ISOMD pin low). Port A on de
-
vices S2 and S3
is configured in isoSPI mode (ISOMD pin
high). Port B on S1 is connected to Port A on S2. Port B
on S2 is connected to Port A on S3. The microcontroller
communicates to the stack through Port A on S1.
Waking Up Serial Interface
1. Send a dummy byte. The activity on CSB and SCK will
wake up the serial interface on device S1.
2. Wait for the amount of time 3 • t
WAKE
in order to power
up all devices S1, S2 and S3.
For large stacks where some devices may go to the IDLE
state after waking, apply steps 3 and 4:
3. Send a second dummy byte.
4. Wait for the amount of time 3 • t
READY
5. Send commands
Write Configuration Registers
1. Pull CSB low
2. Send WRCFG command (0x00 0x01) and its PEC (0x3D
0x6E)
3. Send CFGR0 byte of device S3, then CFGR1(S3), …
CFGR5(S3), PEC of CFGR0(S3) to CFGR5(S3)
4. Send CFGR0 byte of device S2, then CFGR1(S2), …
CFGR5(S2), PEC of CFGR0(S2) to CFGR5(S2)
5. Send CFGR0 byte of device S1, then CFGR1(S1), …
CFGR5(S1), PEC of CFGR0(S1) to CFGR5(S1)
6. Pull CSB high, data latched into all devices on rising
edge of CSB
Table 46. Memory Bit Descriptions