LTC6804-1/LTC6804-2
58
680412fc
For more information www.linear.com/LTC6804-1
applicaTions inForMaTion
SIMPLE LINEAR REGULATOR
The LTC6804 draws most of its power from the V
REG
input
pin. 5V ±0.5V should be applied to V
REG
. A regulated DC/
DC converter can power V
REG
directly, or the DRIVE pin
may be used to form a discrete regulator with the addition
of a few external components. When active, the DRIVE
output pin provides a low current 5.6V output that can
be buffered using a discrete NPN transistor, as shown in
Figure 28. The collector power for the NPN can come from
any potential of 6V or more above V
–
, including the cells
being monitored or an unregulated converter supply. A
100Ω/100nF RC decoupling network is recommended for
the collector power connection to protect the NPN from
transients. The emitter of the NPN should be bypassed
with a 1µF capacitor. Larger capacitor values should be
avoided because they increase the wake-up time of the
LTC6804. Some attention to the thermal characteristic
of the NPN is needed, as there can be significant heating
with a high collector voltage.
Figure 28. Simple V
REG
Power Source Using
NPN Pass Transistor
V
IN
BOOST
LT3990
SWEN/UVLO
PG
RT
0.22µF
22pF
374k
f = 400kHz
22µF
2.2µF
IN
62V
V
REG
5V
1M
316k
33µH
BD
FB
GND
OFF ON
680412 F29
1µF
100Ω
680412 F28
WDT
DRIVE
V
REG
SWTEN
V
REF1
V
REF2
GPIO5
GPIO4
V
–
V
–
GPIO3
1µF
1µF
LTC6804
NSV1C201MZ4
IMPROVED REGULATOR POWER EFFICIENCY
To minimize power consumption within the LTC6804, the
current drawn on the V
+
pin has been designed to be very
small (500µA). The voltage on the V
+
pin must be at least
as high as the top cell to provide accurate measurement.
The V
+
and V
REG
pins can be unpowered to provide an
exceptionally low battery drain shutdown mode. In many
applications, the V
+
will be permanently connected to
the top cell potential through a decoupling RC to protect
against transients (100Ω/100nF is recommended).
For better running efficiency when powering from the cell
stack, the V
REG
may be powered from a buck converter
rather than the NPN pass transistor. An ideal circuit for
this is based on the LT3990 as shown in Figure 29. A 1k
resistor should be used in series with the input to prevent
inrush current when connecting to the stack and to reduce
conducted EMI. The EN/UVLO pin should be connected to
DRIVE so that the converter sleeps along with the LTC6804.
The LTC6804 watchdog timer requires V
REG
power to
timeout. Therefore, if the EN/UVLO pin is not connected
to DRIVE, care must be taken to allow the LTC6804 to
timeout first before removing V
REG
power; otherwise the
LTC6804 will not enter sleep mode.
Figure 29. V
REG
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