Linear Technology LTC6804-1 - Page 32

LTC6804-1/LTC6804-2
32
680412fc
For more information www.linear.com/LTC6804-1
operaTion
Table 17. Write Codes for ICOMn[3:0] and FCOMn[3:0] on SPI Master
CONTROL BITS CODE ACTION DESCRIPTION
ICOMn[3:0]
1000 CSBM low Generates a CSBM Low Signal on SPI Port (GPIO3)
1001 CSBM high Generates a CSBM High Signal on SPI Port (GPIO3)
1111 No Transmit Releases the SPI Port and Ignores the Rest of the Data
FCOMn[3:0]
X000 CSBM low Holds CSBM Low at the End of Byte Transmission
1001 CSBM high Transitions CSBM High at the End of Byte Transmission
Table 16. Write Codes for ICOMn[3:0] and FCOMn[3:0] on I
2
C Master
CONTROL BITS CODE ACTION DESCRIPTION
ICOMn[3:0]
0110 START Generate a START Signal on I
2
C Port Followed By Data Transmission
0001 STOP Generate a STOP Signal on I
2
C port
0000 BLANK Proceed Directly to Data Transmission on I
2
C Port
0111 No Transmit Release SDA and SCL and Ignore the Rest of the Data
FCOMn[3:0]
0000 Master ACK Master Generates an ACK Signal on Ninth Clock Cycle
1000 Master NACK Master Generates a NACK Signal on Ninth Clock Cycle
1001 Master NACK + STOP Master Generates a NACK Signal Followed by STOP Signal
If the bit ICOMn[3] in the COMM register is set to 1 the
part becomes an I
2
C master and if the bit is set to 0 the
part becomes a SPI master.
Table 16 describes the valid write codes for ICOMn[3:0]
and FCOMn[3:0] and their behavior when using the part
as an I
2
C master.
Table 17 describes the valid codes for ICOMn[3:0] and
FCOMn[3:0] and their behavior when using the part as
a SPI master.
Note that only the codes listed in Tables 16 and 17 are
valid for ICOMn[3:0] and FCOMn[3:0]. Writing any other
code that is not listed in Tables 16 and 17 to ICOMn[3:0]
and FCOMn[3:0] may result in unexpected behavior on
the I
2
C and SPI ports.
COMM Commands
Three commands help accomplish I
2
C or SPI communica-
tion to the slave device: WRCOMM, STCOMM, RDCOMM
WRCOMM Command:
This command is used to write data
to the COMM register. This command writes 6 bytes of
data to the COMM register. The PEC needs to be written
at the end of the data. If the PEC does not match, all data
in the COMM register is cleared to 1’s when CSB goes
high. See the section Bus Protocols for more details on a
write command format.
STCOMM Command: This command initiates I
2
C/SPI com-
munication on the GPIO ports. The COMM register contains
3 bytes of data to be transmitted to the slave. During this
command, the data bytes stored in the COMM register are
transmitted to the slave I
2
C or SPI device and the data
received from the I
2
C or SPI device is stored in the COMM
register. This command uses GPIO4 (SDA) and GPIO5
(SCL) for I
2
C communication or GPIO3 (CSBM), GPIO4
(SDIOM) and GPIO5 (SCKM) for SPI communication.
The STCOMM command is to be followed by 24 clock
cycles for each byte of data to be transmitted to the slave
device while holding CSB low. For example, to transmit 3
bytes of data to the slave, send STCOMM command and
its PEC followed by 72 clock cycles. Pull CSB high at the
end of the 72 clock cycles of STCOMM command.
During I
2
C or SPI communication, the data received from
the slave device is updated in the COMM register.