Linear Technology LTC6804-1 - Page 61

LTC6804-1/LTC6804-2
61
680412fc
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EXPANDING THE NUMBER OF AUXILIARY
MEASUREMENTS
The LTC6804 provides five GPIO pins, each of which is
capable of performing as an ADC input. In some applica
-
tions there is need to measure more signals than this, so
one means of
supporting higher signal count is to add
a MUX circuit such as shown in Figure 32. This circuit
digitizes up to sixteen source signals using the GPIO1
ADC input and MUX control is provided by two other
GPIO lines configured as an I
2
C port. The buffer amplifier
provides for fast settling of the selected signal to increase
the usable conversion rate.
INTERNAL PROTECTION FEATURES
The LTC6804 incorporates various ESD safeguards to en
-
sure a robust performance. An equivalent circuit showing
the specific protection structures is shown in Figure
33
.
While pins 43 to 48 have different functionality for the
-1 and -2 variants, the protection structure is the same.
Zener-like suppressors are shown with their nominal clamp
voltage, other diodes exhibit standard PN junction behavior.
Figure 32. MUX Circuit Supports Sixteen Additional Analog Measurements
Figure 33. Internal ESD Protection Structure of LTC6804
applicaTions inForMaTion
periodic or higher oversample rates are in use, a differential
capacitor filter structure is adequate. In this configuration
there are series resistors to each input, but the capacitors
connect between the adjacent C pins. However, the dif
-
ferential capacitor sections interact. As a result, the filter
response is less consistent and results in less attenuation
than predicted by the RC, by approximately a decade. Note
that the capacitors only see one cell of applied voltage (thus
smaller and lower cost) and tend to distribute transient
energy uniformly across the IC (reducing stress events on
the
internal protection structure). Figure 34 shows the two
methods schematically. Basic ADC accuracy varies with R,
C as shown in the Typical Performance curves, but error is
minimized if R = 100Ω and C = 10nF. The GPIO pins will
always use a grounded capacitor configuration because
the measurements are all with respect to V
–
.
Figure 34. Input Filter Structure Configurations
680412 F33
LTC6804
10k
12V
C12
S12
12V
10k
12V
C11
S11
12V
10k
12V
C10
S10
12V
10k
12V
C9
S9
12V
10k
12V
C8
S8
12V
10k
12V
C7
S7
12V
10k
12V
C6
S6
12V
10k
12V
C5
S5
12V
10k
12V
C4
S4
12V
10k
12V
C3
S3
12V
10k
12V
C2
S2
12V
10k
12V
25Ω
C1
S1
12V
C0
V
–
V
–
30V
30V
30V
30V
30V
30V
GPIO1
12V
GPIO2
12V
GPIO3
12V
GPIO4
GPIO5
12V
V
REF2
12V
12V
V
REF1
12V
SWTEN
12V
V
REG
12V
DRIVE
12V
WDT
12V
ISOMD
12V
CSB
12V
SCK
12V
SDI
12V
SDO
12V
IBIAS/A0
12V
ICMP/A1
12V
IMB/A2
12V
IPB/A3
12V
V
+
NOTE: NOT SHOWN ARE PN DIODES TO ALL OTHER PINS FROM PIN 31
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
32
33
31
30
29
28
27
25
26
12
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
680412 F34
CELL2
V
–
C2
10nF
BATTERY V
–
100Ω
Differential Capacitor Filter
BSS308PE
33Ω
3.3k
CELL1
C1
S2
S1
LTC6804
LTC6804
S2
S1
10nF
10nF
100Ω
BSS308PE
33Ω
100Ω
C0
3.3k
CELL2
V
–
C2
BATTERY V
–
100Ω
Grounded Capacitor Filter
BSS308PE
33Ω
3.3k
*
CELL1
C1
100Ω
BSS308PE
*6.8V ZENERS RECOMMENDED IF C > 100nF
33Ω
C0
C
C
C
3.3k
*
*
100Ω