Linear Technology LTC6804-1 - Page 9

LTC6804-1/LTC6804-2
9
680412fc
For more information www.linear.com/LTC6804-1
elecTrical characTerisTics
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
isoSPI Timing Specifications (See Figure 19)
t
8
SCK Falling Edge to SDO Valid (Note 5)
l
60 ns
t
9
SCK Rising Edge to Short ±1
Transmit
l
50 ns
t
10
CSB Transition to Long ±1 Transmit
l
60 ns
t
11
CSB Rising Edge to SDO Rising (Note 5)
l
200 ns
t
RTN
Data Return Delay
l
430 525 ns
t
DSY(CS)
Chip-Select Daisy-Chain Delay
l
150 200 ns
t
DSY(D)
Data Daisy-Chain Delay
l
300 360 ns
t
LAG
Data Daisy-Chain Lag (vs Chip-
Select)
l
0 35 70 ns
t
6(GOV)
Data to Chip-Select Pulse Governor
l
0.8 1.05 µs
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. The test conditions are V
+
= 39.6V, V
REG
= 5.0V unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The ADC specifications are guaranteed by the Total Measurement
Error specification.
Note 3: The ACTIVE state current is calculated from DC measurements.
The ACTIVE state current is the additional average supply current into
V
REG
when there is continuous 1MHz communications on the isoSPI ports
with 50% data 1’s and 50% data 0’s. Slower clock rates reduce the supply
current. See Applications Information section for additional details.
Note 4: These timing specifications are dependent on the delay through
the cable, and include allowances for 50ns of delay each direction. 50ns
corresponds to 10m of CAT-5 cable (which has a velocity of propagation of
66% the speed of light). Use of longer cables would require derating these
specs by the amount of additional delay.
Note 5: These specifications do not include rise or fall time of SDO. While
fall time (typically 5ns due to the internal pull-down transistor) is not a
concern, rising-edge transition time t
RISE
is dependent on the pull-up
resistance and load capacitance on the SDO pin. The time constant must
be chosen such that SDO meets the setup time requirements of the MCU.
Note 6: V
+
needs to be greater than or equal to the highest C(n) voltage for
accurate measurements. See the graph Top Cell Measurement Error vs V
+
.