Marantz CD-7 - Page 7

Q304 : TDA1315H
SYMBOL | PIN | PADCELL DESCRIPTION
RCai 1 E029 | PLL loop filter input
Viet 2 E029 decoupling internal reference voltage output
Vppa 3 E008 analog supply voltage
Vssa 4 E004 analog ground
L!ECIN1 5 E007 high sensitivity IEC input
IECINO 6 IPP04 | TTL level IEC input
lECSEL 7 1UP04 | select IEC input 0 or 1 (0 = IECINO; 1 = IECIN1); this input has an internal pull-up
resistor
IECO 8 OPFH3 | digital audio output for optical and transformer link
IECOEN 9 IUP04 | digital audio output enable (0 = enabled; 1 = disabled/3-state); this input has an
internal pull-up resistor
TESTB 10 IPP04 | enable factory test input (0 = normal application; 1 = scan mode)
TESTC ah IPPO04 | enable factory test input (0 = normal application; 1 = observation outputs)
UNLOCK 12 | OPP41A | PLL out-of-lock (0 = not locked; 1 = locked); this output can drive an LED
FS32 13 | OPP41A | indicates sample frequency = 32 kHz (active LOW); this output can drive an LED
FS44 14 | OPP41A | indicates sample frequency = 44.1 kHz (active LOW); this output can drive an LED
FS48 15 | OPP41A | indicates sample frequency = 48 kHz (active LOW); this output can drive an LED
CHMODE 16 | OPP41A | use of channel status block (0 = professional use; 1 = consumer use); this output
can drive an LED
Vppp2 17 E008 digital supply voltage 2
Vssp2 18 E009 digital ground 2
RESET 19 IDPO9 | initialization after power-on, requires only an external capacitor connected to Vppp;
this is a Schmitt-trigger input with an internal pull-down resistor
PD 20 1PP04 | enable power-down input in the standby mode (0 = normal application; 1 = standby
mode)
| CTRLMODE 21 !UP04 | select microcontroller/stand-alone mode (0 = microcontroller; 1 = stand-alone); this
input has an internal pull-up resistor
LADDR 22 IPP04 | microcontroller interface address switch input (0 = 000001; 1 = 000010)
LMODE 23 IPPO9 | microcontroller interface mode line input
LCLK 24 IPPO9 | microcontroller interface clock line input
LDATA 25 1OF24 | microcontroller interface data line input/output
STROBE 26 IDP04 _| strobe for control register (active HIGH); this input has an internal pull-down resistor
UDAVAIL 27 OPF23 | synchronization for output user data (0 = data available; 1 = no data)
TESTA 28 IPP04 | enable factory (scan) test input (0 = normal application; 1 = test clock enable)
COPY 29 | OPP41A | copyright status bit (0 = copyright asserted; 1 = no copyright asserted); this output
can drive an LED
INVALID 30 10D24 | validity of audio sample input/output (0 = valid sample; 1 = invalid sample); this pin
has an internal pull-down resistor
DEEM 31 OPF23 | pre-emphasis output bit (0 = no pre-emphasis; 1 = pre-emphasis)
MUTE 32 1UP04 | audio mute input (0 = permanent mute; 1 = mute on receive error); this pin has an
internal pull-up resistor
2SSEL 33 |UP04 | select auxiliary input or normal input in transmit mode
SDAUX 34 |PP04 | auxiliary serial data input; |?S-bus
SD 35 | 10F24 | serial audio data input/output; \?S-bus
ws 36 1OF24 | word select input/output; I?S-bus
SCK 37 |OF29 _| serial audio clock input/output; |?S-bus
2S0EN 38 1UP04 | serial audio output enable (0 = enabled; 1 = disabled/3-state); this input has an
internal pull-up resistor
SYSCLKI 39 IPPO9 | system clock input (transmit mode)
SYSCLKO 40 OPFA3 | system clock output (receive mode)
Vssp1 41 E009 digital ground 1
Vppp1 42 E008 digital supply voltage 1 .
CLKSEL 43 1UP04 | select system clock (0 = 384f,; 1 = 256f,); this input has an internal pull-up resistor
RCint 44 E029 integrating capacitor output
QD03/QD53 : TDA1541A/S2
PINNING
SYMBOL PIN DESCRIPTION
LE/wst) 1 latch enable input/ word select
input
BCK) 2 bit clock input
DATA L 3 data left channel input/ data
/DATA) input (selected format)
DATA R() 4 data right channel input
GND(A) 5 analog ground
AOR 6 right channel output
DECOU 7 to 13 | decoupling
GND (D) 14 digital ground
Vpp2 15 -15 V supply voltage
COSC 16,17 | oscillator
DECOU 18 to 24 | decoupling
AOL 25 left channel output
Vpp1 26 —5 V supply voltage
OB/TWC"") 27 | mode select input
Vpp 28 +5 V supply voltage
Note
1. See Table 1 data selection input.
Q507/Q509 : DSP56004
16-Bit Bus
24-Bit Bus
External
Memory
Interface
Serial
Host
Interface
General
Purpose
Input’
24-Bit
DSP56000
Core
Address
Generation
Internal
Data
Bus
Switch
peo
Data ALU
24 x 24 + 56 — 56-bit MAC
Two 56-Bit Accumulators
Program
Decode
Controller
*Refer to Table 1 for memory configurations.
Power Inputs DSP56004
ni MOSI/HAO
Veco —5 Port B SS/HA2
Vecs
————>
Serial
Host
MISO/SDA
Ground Interface SCK/SCL
GNDp
——___
+]
HREQ
GNDg >
GND, --————
Port C
Serial Audio
Interface
wsR
PCAP
SCKR
PINIT SpI0
EXTAL spit
WST
SCKT
MAODMA14 SDOO
MDODMD7 SDO1
MA15/MCS3
MA16/MCS2/MCAS
sDO2
PortA
MA17/MCS1/MRAS External Memory
MCSO Interface
MWA
GPIOODGPIO3
RD
MODC/NMI DSCK/OS1
MODB/IRQB Mode/Interrupt 7 DSI/OSO
peas Control Once
MODA/IRQA
Port
DSO
RESET Reset DR
80 signals
QF01 : .PD78076 MAIN
Pin No. |Port Name |Function|In/Out|Active; To/From |Description
1 STRB P120 | Out | High| Q304 [Strobe signal for control resister for Q304(TDA1315H)
2 LMOD P121_| Out | Low Q304__|Interface mode line for Q304(TDA1315H)
3 OPEN P122 =o
4 GND. P123 GND___|GND
5 FS32 P124 In_| Low Q304_ _|Sampling frequency input __ (L = 32KHz Receiving)
6 FS48 P125 In__| Low Q304__|Sampling frequency input (L = 48KHz Receiving)
7__\COAX/OPT,_P126 | Out | Low Q304__ {Digital input select signal_(L = Optical , H = Coaxal)
8 DMUT P127_| Out | Low Q304__ {Digital muting control signal for Q304(TDA1315H)
9 GND IC GND__|GND
10 SMHzXTAL X2 XFO1__|Clock out (5MHz)
11 |SMHzXTAL X11 XFO1__|Clock in (5MHz)
12 +5V Vdd +5V___|Power supply +5V
13 OPEN xT2 = —
14 +5V XT1 +5V___|Power supply +5V
15 REST | RESET| In _| Low| QF02__|Reset signal input for QFO2
16 RCS5I INTPO | In | 4 # ZY01__|Remote control signal input for ZY01
17 OPEN INTP1 = eecee
18 CD7R P02 | Out | Low Q102__|CD7 Reset signal for Q102(SAA7372GP)
19 SILD Po3_ | Out | Low Q102__|Strobe signal for servo part of Q102(SAA7372GP)
20 RAB7 PO3__| Out | Low Q102__|Strobe signal for digital part of Q102(SAA7372GP)
21 LOCK | INTPS |_ In_| Low Q304__ [Unlock signal of Q304(TDA1315H)
22 MSCP_| INTP6 | In_| Low GND ___|GND
23 +5V Avdd +5V___|Power supply +5V
24 +5V AvrefO_| In +5V___|Power supply +5V
25 KEYO ANIO In_| Level|Tact Switch| Key Sensor
26 KEY1 ANI1 In_|Level|Tact Switch Key Sensor
27 KEY2 ANI2 In_|Level|Tact Switch|Key Sensor
28 GND ANI3 GND [GND
29 MUTE ANI4 | Out | High| Q507__|Mute signal for DSP Q507(DSP56004)
30 PAUS ANI5_| Out | High | Q507___|Mute of pause on time for DSP Q507(DSP56004)
31 OPEN ANI6 (CD7L) _|-----
32 RELY2 ANI7_| Out | High QY51__|Display on/off control signal (L = off, H = on)
33 GND Avss GND___|GND
34 OPEN P130__ {In/Out Se ttt
35 OPEN P131_ | Out seem
36 +5V Avref In +5V___| Power supply +5V
37 STRD P70__| Out | Low QY01__/|Strobe signal for QY01
38 SIOD S02 | Out |} # QY01__|Serial data for QY01
39 CLKD SCK2 | Out | Low QY01__|Serial clock for QY01
40 GND Vss GND ___|GND
41 OPEN si In - =
42 OPEN $O1 =
43 OPEN SCK1 —_
44 OPEN P23 ae
45 OPEN P24 =
46 OPEN SBO =
47 OPEN SBi__|In/Out —- =
48 SDA SCKO_| Out Q102/Q304/ Serial data signal for Q102/Q304
49 SCL AO Q102/Q304 Serial clock signal for Q102/Q304
50 OPEN Al =
51 OPEN A2 —
52 OPEN A3 =
53 OPEN A4 _
54 OPEN AS =
55 OPEN AG =
56 OPEN AZ = |--
57 GND DO GND__|GND
58 GND D1 GND___|GND
59 GND D2 GND__|GND
60 GND D3 GND___|GND
61 GND D4 GND___|GND
62 GND D5 GND___|GND
63 GND D6 GND __|GND
64 GND D7 GND__|GND.
65 OPEN A8& = =:
66 OPEN AQ =
67 OPEN A10 =
68 OPEN Alt Se
69 OPEN Ai2 = =:
70 OPEN A13 = ---
71 GND Vss GND ___|GND
72 OPEN Al4 (RA12)_|-----
73 RA11 A1i5 | Out | High Q506__| Audio data select signal output (L = 16Bit)
74 16WD P60 In__| Low GND___|Audio data select signal input _(L = 16Bit)
75 FMUT P61 Out | High | QNO5 [Mute of switching on time killer
76 RSD2 P62 | Out | Low |Q309,Q509) Reset of Q309,Q509
77 RSD1 P63 | Out | Low Q507__|Reset of Q507
78 NSSH RD Out | Low |Q508,QY10 Noise shaper on/off signal (L = on, H = off)
79 FIL3 WR_| Out | High |Q508,QY09[Filter 3 select signal _(H = select of filter 3)
80 FIL2 P66 | Out | High |Q508,QY08Filter 2 select signal _(H = select of filter 2)
81 FIL1 P67__| Out | High QY07__|Filter 1 select signal __ (H = select of filter 1)
82 OPTI P100 | In | High| Q303 [Optical input select (H = OPT, L = COAX1)
83 OPEN TO6 eco
84 OPEN | P102 —
85 RELY1 | P103 | Out |High| D301
86 MSL1 P30 In__| High | High Level
87 MSL2 P31 In_| Low | GND Level
88 OPEN P32 = =
89 CDRW. P33 _| Out | High NC |-----
90 SLSW P34 In_| Low | VAM1201 |Sledge detect switch (L = in end)
91 TROS P35 In_ | Low | TRAY [Tray in/out detect switch (L = out end)
92 TRIS P36 In_| Low| TRAY __|Tray in/out detect switch (L = in end)
93 TRUS P37 In_| Low|_TRAY {Tray up/down detect switch (L = up end)
94 TRDS P90 In_| Low | TRAY__/Tray up/down detect switch (L = down end)
95 TROM P91 Out | High || QM10__ [Tray motor control signal_(H = tray out)
96 TRIM P93 _| Out | High | QMO09 {Tray motor control signal _(H = tray in)
97 TRDM P94 | Out | High | QM12_ [Tray motor control signal_(H = tray down)
98 _| TRUM P95_| Out | High} QM11__|Tray motor control signal_(H = tray up)
99 AMUT P95 | Out | Low NC |-----
100 | DA/CD P96__| Out | Low Q504__|Mode select_(L = D/A Mode , H = CD Mode)