Marantz CD-7 - Block Diagram

7. BLOCK DIAGRAM
SUB CHASSIS
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POWER INPUT
—_——+o
MONITOR
AIOE
Rel]
CO MECHANISM = VANI252
SS ise:
TURNTABLE
MOTOR
ae
ZYO1
FOC. MOTOR
CURENT
CONTROL
=a
v4
2, 03 \ 1923
Bl. 8;
24, 85
1 R-OUT
MOTOR OBRIVE
& HF AMP
| atos
| Tea7o73aT
FOC DRIVE
CLV DRIVE }
272
BECODE & SERVO
Q102_SAA7372GP
8 i
AND
THAI302T
CURRENT AMP
AND
EQ HF AMPLIFIER
W
QFO1
16 RCS]
RELAY
85
MASTER UPC SERVO ANA OTHER CONTROL
SUBCODE
NS
48 SCL 19 SILO
47 SBA_ 20 RAB/C7
18 CO7 Es)
RELAY!
32
MUTE (ON/OFF) 8ISPLAY (ON/OFF)
+5V -SV
POWER
MUTING RELAY
CONTROL,
~17V -24V0 +11 -11V
POWER SUPPLY
VOLTAGE REGULATOR
VOLTAGE FALLING
DETECT
BIGITAL SERVO
PROCESSOR
BEMOBULATOR
ERROR CORRECTION
8. FLAG No.
DIFFERENTIAL
(No. [Flag Name Function
0 | MT-OUT /Motor Drive Output
|_ 1 | HF-OUT |TDA1302T HF signal output
BAC bere 3 HF-HPF_ {HF Signal HPF Output
SFC CLK & BATA SELECT OIF GBOS THAISS1A/S2 4 | LDON Lazer Diotis Control Signal
@507,Q509 BIGTAL FILTER (OSPS6004) 5
6 RA Radial Motor Control Signal(PDM)
oO 7 FO Focus Motor Control Signal(PDM)
FILTER/NOISE SHAPER/OVER SAMPLING = 8 SL___[Slegde Motor Control Signal(PDM)
ma 10 | _DIGO [Digital Audio Output Signal
ii qe 11] CDR7_|CD7(SAA7372) Reset Pulse
FRGO,
BCKO
wor
V3
J
=
12
SILD__|CD7(SAA7372)
Servo
Parte
enable
Signal
ATS, LRCO 1h Aas D> 2 [13] RAB7 _|CD7(SAA7372) Decorde and DSP parte enable signal
= : 14| SCDC_|CD7(SAA7372) data clock out signal
ok TCW125FU N 115 | WCDC_ |CD7(SAA7372) data word clock out signal
Shes t 6 SIIO___|Servo peb and Main pcb comunicateing signal
+ 17
rbd tal HOAM 6) 18 | __LRCK _|SM5844AF(Q309) word clock signal
p 2X! 5X2 - 19
a 3 20
ms
21
DADC
_|CD7(SAA7372)
data
out(16bit)
signal
Biv
7681s
QN53
TAAIS41A/52
22
|
36MHz_|Sampling
frequency
48KHz/32KHz
Master
clock
3 beeen 23 | 33MHz_|Sampling frequency 44KHz Master clock
X301. X302 24 SDA ___ [From CPU(QF01) TO TDA1315H(Q304) data signal
25 SCL [From CPU(QF01) TO TDA1315H(Q304) clock signal
B8sts Oo 26
1 <= 27| REST |CPU(QF01) Power on reset
SAME LNG CONVERTOR wa rE 28 | __RCDK __|Main peb SIIO Latch pulse for(Q501,Q502, 0503)
(SMS844AF) p fi ARs oo 29 [7 RCDG_|SERVO PCB SIIO Latch pulse for QFO6
ZG — = 30
142,81 Ci o ES ot
eS — @
faa) =) 32
= 33
ma d 34
oO
Seetlie rf 35 | OSG IGPUIGEOT) self clock
kK PU(QF01) self clock
2 Q304 TDA1315 jibe cu
8 IECO
LLLLLL
y,
FA
8
COAX
5)
[Tir
|
aa
!
©
39
Y BIGITAL BIO RECEIVER rs 411 LOCK —|TDA1315H(Q304) unlock delayed output signal
ZY 42 | EMPA |TDA1315H(Q304) Deemphasis output signal
Ys VELA: 7 lGi/DIG2 13 F532 OFT 6 43 | DACD _|CD7(SAA7372) data out signal
12 LOCK, 14 FS44
38
BA/CD
15
F548
RESET
44
[
Z
$302,
(16/20B1T.
SW)
45
5
BIG
COAXI
46
is hz IN [47
+
CORT
coat
Ait
48
|
_DMUT
_
{from
CPU(QFO1)
to
TDA1315H(Q304)
muting
signal
5 F932 fe 49
0p See Py (M) BIG COAX2 50 FS32 _|TDA1315H(Q304) 32k Sampling detected signal
wort gel 1 TRAY MOTOR 0377 arewi25eU IN 51| F844 __|TDA1315H(Q304) 44.1k Sampling detected signal
| | iwaur 521 FS48__|TDA1315H(Q304) 48k Sampling detected signal
py
BRIVE
OPT/COAX
53
SD
__/TDA1315H(Q304)
data
output
signal
(M) OPT 54| WS _|TDA1315H(Q304) Word select output signal
SWITCH IN 55 SCK___|TDA1315H(Q304) data clock output signal
se 56 FRQ2__|CD7(SAA7372) Operating clock out signal
57 | UNLOCK |TDA1315H(Q304) unlock output signal
ayo! Sa ae $301 | 58
bskslaalil . i ella ei 59 | COAX2_|Digtal /O input COAX2 signal
KEY MATRIX JTO1 -80 OPTO__|Digtal 1/O input OPTICAL signal
1h KEY? PLAY/STOP/PAUSE/NEXT/PREV 10US BIG COAX 62
10, KEY! \ OP/CLOSE VFI VE2 OUT 63
BISPLAY ARIVER N o4
SN
row
oigo_|
BIGTAL
ck
dae
66
|__
OUT+
_
Correct
phase
AUDIO
SIGNAL
IS m8 QQ Sor aunees ais 67 OUT-__Inverse phase AUDIO SIGNAL
69 | REMU_ [Relay mute by POWER ON/OFF and selecting FILTER mode
70
WYO 6-BT-97ZK) a
ye BIG OPT 72
Io} A OUT 73
74
75
76
| 77
78
79| 768FS__|Master clock selecting output
80 | 256FS_|Master clock divided output
81 128FS __|Master clock divided output
82 4FS 176.4KHz before Word select signal
83 | WSDA_ [Word select for DSP(Q509) and DAC(QD03,QD53)_ 176.4KHz
84 | FMUT __|Filter select switching on time unenable for DAC
85 | CLDA |DSP(Q509) data clock signal
86 | BCEN |DSP(Q509) data clock enable signal for DAC
87| BCDA __|for DAC(QD03,QD53) data clock 5.6448MHz
88
89
90
91
92
93
| 94
95
| 96
97
98
99
10