Marantz PMD620 - Top Panel Features

32
Q005 : MT48LC4M16A2B4-7E
12
RAS#
CAS#
ROW-
ADDRESS
MUX
CLK
CS#
WE#
CKE
CONTROL
LOGIC
COLUMN-
ADDRESS
COUNTER/
LATCH
MODE REGISTER
10
COMMAND
DECODE
A0–A11,
BA0, BA1
DQM
12
ADDRESS
REGISTER
14
1024
(x4)
4096
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
COLUMN
DECODER
BANK0
MEMORY
ARRAY
(4,096 x 1,024 x 4)
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
SENSE AMPLIFIERS
BANK
CONTROL
LOGIC
DQ0–DQ3
4
4
DATA
INPUT
REGISTER
DATA
OUTPUT
REGISTER
4
12
BANK1
BANK2
BANK3
12
10
2
1 1
2
REFRESH
COUNTER
BLOCK DIAGRAM
A
B
C
D
E
F
G
H
J
12345678
VSS
DQ14
DQ12
DQ10
DQ8
DQMH
NC/A12
A8
V
SS
DQ15
DQ13
DQ11
DQ9
NC
CLK
A11
A7
A5
V
SSQ
V
DDQ
V
SSQ
VDDQ
V
SS
CKE
A9
A6
A4
V
DDQ
V
SSQ
V
DDQ
VSSQ
V
DD
CAS#
BA0
A0
A3
DQ0
DQ2
DQ4
DQ6
DQML
RAS#
BA1
A1
A2
V
DD
DQ1
DQ3
DQ5
DQ7
WE#
CS#
A10
V
DD
9
X16 VFBGA BALL ASSIGNMENT (TOP VIEW, BALL DOWN)
Notes: The balls at A4, A5, and A6 are absent from the physical package. They are
included to illustrate that rows 4, 5, and 6 exist but contain no solder balls.