Marantz PMD620 - Page 34

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Q207 : M66592FP
CPU bus interface
D15-7,D6-1(/AD6-1),D0
A6/ALE,A5-1
CS_N
RD_N
WR0_N
WR1_N
MPBUS
Interrupt / SOF output
INT_N
SOF_N
DMA interface
DREQ0_N
DACK0_N
DEND0_N
DREQ1_N
DACK1_N/DSTB0_N
DEND1_N
Split bus
SD7-0
System control
RST_N
TEST
16
6
Clock
XIN
XOUT
VBUS monitor input
VBUS
USB interface
DP, DM
Reference resistance
REFRIN
M66592
8
2
Figure 1.3 Pin function configuration diagram
PIN FUNCTION CONFIGURATION DIAGRAM
A
6(/ALE), A5-1,
D15-7, D6-1(/AD6-1), D0,
CS_N, RD_N,
WR0_N,WR1_N
MPBUS
C
PU bus interface
INT_N, SOF_N
CPU_IF_Reg
Int_Ctrl
Interrupt /SOF output
Ground AFE Ground
VDDVIF
A
FEA33V, AFED33V
A
FEA15V, AFED15V
A
FEA33G,AFED33G
A
FEA15G,AFED15G
DGND
Buf_Mem
BIU
FIFO_Port
Pipe_Ctrl
Prctl_Eng
AFE
USB interface
S
PLIT bus
SD7-0
DP, DM
DREQ0_N, DREQ1_N
DACK0_N,
DACK1_N/DSTB0_N,
DEND0_N, DEND1_N
DMA interafce
VBUS monitor input
VBUS
S
ystem control
RST_N, TEST
Renerence registor
REFRIN
Clock
XIN, XOUT
SIE
Figure 1.4 Block diagram
BLOCK DIAGRAM