Microchip Technology dsPIC33 - Page 15

 2010-2013 Microchip Technology Inc. DS30009740B-page 15
Liquid Crystal Display (LCD)
Register 5-2: LCDREG: LCD Voltage Regulator Control Register
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
CPEN
— — — — — — —
bit 15 bit 8
U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-0 R/W-0
— — BIAS2 BIAS1 BIAS0 MODE13 CKSEL1 CKSEL 0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CPEN: LCD Charge Pump Enable bit
1 = Charge pump enabled; highest LCD Bias voltage is 3.6V
0 = Charge pump disabled; highest LCD Bias voltage is AV
DD
bit 14-6 Unimplemented: Read as ‘0’
bit 5-3 BIAS<2:0>: Regulator Voltage Output Control bits
111 = 3.60V peak (offset on LCDBIAS0 of 0V)
110 = 3.47V peak (offset on LCDBIAS0 of 0.13V)
101 = 3.34V peak (offset on LCDBIAS0 of 0.26V)
100 = 3.21V peak (offset on LCDBIAS0 of 0.39V)
011 = 3.08V peak (offset on LCDBIAS0 of 0.52V)
010 = 2.95V peak (offset on LCDBIAS0 of 0.65V)
001 = 2.82V peak (offset on LCDBIAS0 of 0.78V)
000 = 2.69V peak (offset on LCDBIAS0 of 0.91V)
bit 2 MODE13: 1/3 LCD Bias Enable bit
1 = Regulator output supports 1/3 LCD Bias mode
0 = Regulator output supports Static LCD Bias mode
bit 1-0 CKSEL<1:0>: Regulator Clock Source Select bits
11 = 31 kHz LPRC
10 =8 MHz FRC
01 =SOSC
00 = LCD regulator is disabled