Micron Xccela Flash - Appendix B: Example Command Sequence

CCM005-1718347970-10451
micron_xccela_zedboard_user_guide.pdf Rev 2.1 4/19 16
Micron
®
Xccela
™
Flash User Guide for ZedBoard
™
Appendix B: Example Command Sequence
XCCELA>>> RDID
ID is 0x2c 5b 1a 10 41 0
XCCELA>>> TUNING D200 0
Set SPI clock frequency to 25MHz
Set drive strength to 18 ohm
Software reset device
Erasing 64B TDP in address 0x00000000 (3 byte address) ...Done!
Writing 64B TDP to address 0x00000000 (3 byte address) ...Done!
Verifying 64B TDP from address 0x00000000 (3 byte address) ...Pass!
TDP pattern is setup successfully!
0x00000000: ff0fff00 ffccc3cc c33cccff fefffeef
0x00000010: ffdfffdd fffbfffb bfff7fff 77f7bdef
0x00000020: fff0fff0 0ffccc3c cc33cccf feffffee
0x00000030: fffdfffd dfffbfff bbfff7ff f77f7bde
Enable Octal DDR mode
Set to 200MHz DDR mode
Set compensation value to 0:
>>>>rd_phase 0 ................................
>>>>rd_phase 1 ................................
>>>>rd_phase 2 ................................
>>>>rd_phase 3 ................................
>>>>rd_phase 4 ................................
>>>>rd_phase 5 ................................
>>>>rd_phase 6 ................................
>>>>rd_phase 7 ................................
>>>>rd_phase 8 ................................
>>>>rd_phase 9 ................................
>>>>rd_phase10 ................................
>>>>rd_phase11 ................................
>>>>rd_phase12 ................................
>>>>rd_phase13 ................................
>>>>rd_phase14 ................................
>>>>rd_phase15 ................................
>>>>rd_phase16 ................................
>>>>rd_phase17 ................................
>>>>rd_phase18 ................................
>>>>rd_phase19 ................................
>>>>rd_phase20 ................................
>>>>rd_phase21 ................................
>>>>rd_phase22 ................................
>>>>rd_phase23 ................................
>>>>rd_phase24 ................................
>>>>rd_phase25 ................................
>>>>rd_phase26 ................................
>>>>rd_phase27 ................................
>>>>rd_phase28 ................................
>>>>rd_phase29 ................................
Set compensation value to 1:
>>>>rd_phase 0 ................................
>>>>rd_phase 1 ................................
>>>>rd_phase 2 ................................
>>>>rd_phase 3 ................................
>>>>rd_phase 4 ................................
>>>>rd_phase 5 ................................
>>>>rd_phase 6 ................................
>>>>rd_phase 7 ................................
>>>>rd_phase 8 ................................
>>>>rd_phase 9 ................................