Structure and Assembly/Disassembly of the Machine
Figure 3-40 Schematic diagram of the main board
The ATGC-DAC circuit mainly uses a DAC to generate the voltage-controlled signal of
the voltage-controlled gain amplifier. In addition, this dual-channel DAC can also
generate a voltage-controlled signal for controlling the PHV variation, and the input signal
of the DAC is provided by EP1S10.
EP1S10F672C7 is the FPGA of the Stratix series made by ALTERA. It features 1M gate,
10,000 LE, 94 blocks of 512bits RAM, 60 blocks of 4Kbits RAM, one block of 512Kbits
DP-3300/DP-3200 Service Manual（V1.1） 3-3
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