Overview
design is used for the hardware support on the functions realized by the system software.
2.1.2.1System CPU
MCF5307 made by MOTOROLA is used as the system CPU, and it features as follows:
1. 8 k bytes uniform cache (i.e. the data are with the instructions)
2. 4 k bytes on-chip SRAM (high speed SRAM, running with the core in the same
frequency without waiting time)
3. integer/fraction product unit (similar to the DSP instruction)
4. hardware division unit
5. system tuning interface
6. supporting synchronous DRAM/asynchronous DRAM
7. four-channel DMA controller
8. two general timers
9. two full-duplex serial ports
10. IIC bus
11. parallel I/O port
12. system integration module (SIM)
In the 90MHz core frequency, the processing capability of the chip 5307 is 75MIPS
(dhrystone 2.1 testing standard), but for the chip 5206, it is 17 MIPS in the frequency of
33MHz. Therefore the operation capability of CPU is greatly boosted up.
2.1.2.2Reset logic
The external reset of the MCF5307 is derived from two sources: watchdog and BDM port.
The both sources can generate the reset signal, and they encounter in the CPLD and
generate the /RSTI signal required by CPU. To ensure the correct reset of other portions
of the system, the /RSTO signal outputted by CPU is used to reset other components.
The CAT24C161 is used as reset/watchdog chip.
3-12 DP-3300/DP-3200 Service Manual（V1.1）
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