Mitsubishi Electric R16MTCPU - Execution of Motion Dedicated PLC Instruction

88
2 MOTION DEDICATED PLC INSTRUCTION
2.3 Precautions
Number of simultaneous acceptances for Multiple CPU dedicated instructions
The number of instructions that can be accepted simultaneously in the Motion CPU is shown in the table below.
*1 The number of simultaneous executions is dependent on the number of CPU dedicated instruction empty blocks on the PLC CPU side.
When more than the above number of instructions are executed by the PLC CPU, even if there is enough area in the CPU
dedicated instruction transmission area, the Motion CPU cannot accept it. In this case, 2100H is set to the complete status
information and abnormal completion occurs.
Execution of Motion dedicated PLC instruction
• Motion dedicated PLC instruction can be executed with a fixed cycle execute type program and interrupt program.
However, the complete device is a pulse-type. If the complete device (M100 in below example) is set, it may not be
recognized during the PLC scan. Therefore, the sequence program should scan for completion of the device and use a set
bit to execute the Motion instruction string.
• The below devices cannot be used as program file registers or local devices.
• When using the Motion dedicated function of the operation control step (Fn/FSn) and servo program (Kn) in Motion CPU, it
is necessary to create a user-defined interlock using WAIT transition (Gn) as shown below.
Instruction Number of simultaneous acceptances
M(P).SFCS/D(P).SFCS 64
M(P).SVST/D(P).SVST 256 instructions total
M(P).SVSTD/D(P).SVSTD
M(P).CHGA/D(P).CHGA
M(P).CHGAS/D(P).CHGAS
M(P).MCNST/D(P).MCNST
M(P).CHGV/D(P).CHGV No limitation
*1
(The command speed and torque limit value of the instructions last executed is valid)
M(P).CHGVS/D(P).CHGVS
M(P).CHGT/D(P).CHGT
M(P).DDWR/D(P).DDWR No limitation
*1
(Processed in the order of issue)
M(P).DDRD/D(P).DDRD
M(P).BITWR/D(P).BITWR
M(P).GINT/D(P).GINT
• Each instruction’s complete device and complete status
• M(P).DDRD/D(P).DDRD instruction of D1 (First device of the self CPU where the reading data is stored.)
MP.SVST H3E1 "J1" K11 M100 D100
M100
Complete
device
Normal complete program
Abnormal complete program
M101
M101
M10
Gn
Kn
Gn