Open Controller
4-6 Theory of Operation
The external SRAM (U0103) as well as the µP’s own internal RAM space are used for temporary
calculations required by the software during execution. All of the data stored in both of these
locations is lost when the radio powers off (See the particular device subsection for more details).
The FLASH EEPROM contains the actual Radio Operating Software. This software is common to all
open architecture radios within a given model type. For example Securenet radios may have a
different version of software in the FLASH EEPROM than a non-secure radio (See the particular
device subsection for more details).
The K1
µ
P provides an address bus of 16 address lines (A0-A15), and a data bus of 8 data lines (D0-
D7). There are also three control lines; CSPROG (U0101-29) to chip select U0102-30 (FLASH
EEPROM), CSGP2 (U0101-28) to chip select U0103-20 (SRAM) and PG7_R_W to select whether
to read or to write. All other chips (ASFIC/PENDULLUM/DAC/FRACN/LCD/LED/optional EEPROM/
OPTION BOARD) are selected by 3 lines of the µP using address decoder U0105. When the µP is
functioning normally, the address and data lines should be toggling at CMOS logic levels.
Specifically, the logic high levels should be between 4.8 and 5.0 V, and the logic low levels should be
between 0 and 0.2 V. No other intermediate levels should be observed, and the rise and fall times
should be <30 ns.
The low-order address lines (A0-A7) and the data lines (D0-D7) should be toggling at a high rate,
i.e., you should set your oscilloscope sweep to 1 us/div. or faster to observe individual pulses. High
speed CMOS transitions should also be observed on the µP control lines.
On the µP the lines XIRQ (U0101-30), MODA LIR (U0101-77), MODB VSTPY (U0101-76) and
RESET (U0101-75) should be high at all times during normal operation. Whenever a data or
address line becomes open or shorted to an adjacent line, a common symptom is that the RESET
line goes low periodically, with the period being in the order of 20 msecs. In the case of shorted lines
you may also detect the line periodically at an intermediate level, i.e. around 2.5 V when 2 shorted
lines attempt to drive to opposite rails.
The MODA LIR (U0101-77) and MODB VSTPY (U0101-76) inputs to the µP must be at a logic 1 for
it to start executing correctly. After the µP starts execution it will periodically pulse these lines to
determine the desired operating mode. While the Central Processing Unit (CPU) is running, MODA
LIR is an open-drain CMOS output which goes low whenever the µP begins a new instruction (an
instruction typically requires 2-4 external bus cycles, or memory fetches).
However, since it is an open-drain output, the waveform rise assumes an exponential shape similar
to an RC circuit.
There are eight analogue to digital converter ports (A/D) on U0101. They are labelled within the
device block as PE0-PE7. These lines sense the voltage level ranging from 0 to 5 V of the input line
and convert that level to a number ranging from 0 to 255 which can be read by the software to take
appropriate action.
For example, U0101-46 is the battery voltage detect line. R0641 and R0642 form a resistor divider
on SWB+. With 30K and 10K and a voltage range of 11 V to 17 V, that A/D port would see 2.74 V to
4.24 V which would then be converted to ~140 to 217 respectively.
U0101-51 is the high reference voltage for the A/D ports on the µP. Resistor R0106 and capacitor
C0106 filter the +5 V reference. If this voltage is lower than +5 V the A/D readings will be incorrect.
Likewise U0101-50 is the low reference for the A/D ports. This line is normally tied to ground. If this
line is not connected to ground, the A/D readings will be incorrect.
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