Frequency Synthesis
4-22 Theory of Operation
In order to generate a high voltage to supply the phase detector (charge pump) output stage at pin
VCP (U8701-32), a voltage of 13 VDC is being generated by the positive voltage multiplier circuitry
(D8701-1-3, C8716, C8717). This voltage multiplier is basically a diode capacitor network driven by
two (1.05MHz) 180 degrees out of phase signals (U8701-9 and -10).
Output LOCK (U8701-2) provides information about the lock status of the synthesizer loop. A high
level at this output indicates a stable loop. IC U8701 divides the 16.8 MHz reference frequency down
to 2.1 MHz and provides it at pin 11. This signal is used as clock signal by the controller.
The serial interface (SRL) is connected to the microprocessor via the data line SPI DATA (U8701-5),
clock line SPI CLK (U8701-6), and chip enable line FRACN CE (U8701-7).
10.3 Voltage Controlled Oscillator (VCO)
The Voltage Controlled Oscillator (VCO) is formed by the colpitts oscillator FET Q8802. Q8802
draws a drain current of 10 mA from the FRAC-N IC super filter output. The oscillator frequency is
half of the desired frequency and mainly determined by L8804, C8809, C8810, C8812 - C8815 and
varactor diodes D8802 / D8803. Diode D8804 controls the amplitude of the oscillator.
A balanced frequency doubler T8821, D8821 converts the oscillator fundamental to the desired
frequency. With a steering voltage from 2.5V to 10.5V at the varactor diodes the full RX and TX
frequency range from 254.9 MHz to 350 MHz is covered.
The doubler output is buffered by Common VCO Buffer Q8831 which draws a collector current of 15
mA from the stabilized 5V (U8891). A bandpass filter composed of L8831, C8832 - C8836, 15 nH
micro-stripline rejects unwanted harmonics at the first and third oscillator fundamental frequency
and matches the output to the following buffer stages. Buffer Q8831 drives the Pre-scaler Buffer
Q8841, the PA Buffers Q8851, Q8852 (Pout = 13dBm) and Mixer Buffer Q8881 (Pout = 10dBm).
Q8841 draws a collector current of 14 mA from the stabilized 5V, Q8851 draws 15mA, Q8852 draws
20 mA and Q8881 draws 18 mA form the FLT 9V3 source. The buffer stages Q8851, Q8881 and the
feedback amplifier Q8841 provide the necessary gain and isolation for the synthesizer loop.
Q8801 is controlled by output AUX3 of U8701 (pin 1) and enables the RX or TX buffer. In RX mode
AUX3 is nearly at ground level, in TX mode about 5V DC. In TX mode, with R8802 pulled to ground
level by Q8801, the modulation signal coming from the FRAC-N synthesizer IC (U8701 pin28)
modulates the VCO via varactor diode D8801 while in RX mode the modulation circuit is disabled by
pulling R8802 to a higher level through R8882.
10.4 Synthesizer Operation
The complete synthesizer subsystem works as follows. The output signal of the VCO (Q8802) is
frequency doubled by doubler D8821 and, buffered by Common VCO Buffer Q8831. To close the
synthesizer loop, the collector of Q8841 is connected to the PREIN port of synthesizer U8701 (pin
20). The buffer output (Q8831) also provides signals for the Mixer Buffer Q8881 and the PA Buffers
(Q8851, Q8852).
The pre-scaler in the synthesizer (U8701) is basically a dual modulus pre-scaler with selectable
divider ratios. This divider ratio of the pre-scaler is controlled by the loop divider, which in turn
receives its inputs via the SRL. The output of the pre-scaler is applied to the loop divider. The output
of the loop divider is connected to the phase detector, which compares the loop divider´s output
signal with the reference signal.The reference signal is generated by dividing down the signal of the
reference oscillator (Y8702).
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