Chapter 3
3-14
Configure DRAM Timing by SPD
Selects whether DRAM timing is controlled by the SPD (Serial Presence
Detect) EEPROM on the DRAM module. Setting to Enabled enables
CAS# Latency, RAS# Precharge, RAS# to CAS# Delay, Precharge Delay
and Burst Length automatically to be determined by BIOS based on the
configurations on the SPD. Selecting Disabled allows users to configure
these fields manually.
CAS# Latency
The field controls the CAS latency, which determines the timing de-
lay before SDRAM starts a read command after receiving it. Setting
options: 2 Clocks and 3 Clocks. 2 Clocks increases system perform-
ance while 3Clocks provides more stable system performance.
RAS# Precharge
This item controls the number of cycles for Row Address Strobe
(RAS) to be allowed to precharge. If insufficient time is allowed for
the RAS to accumulate its charge before DRAM refresh, refresh
may be incomplete and DRAM may fail to retain data. This item
applies only when synchronous DRAM is installed in the system.
Available settings: 2 Clocks, 3 Clocks.
RAS# to CAS# Delay
This field allows you to set the number of cycles for a timing delay
between the CAS and RAS strobe signals, used when DRAM is
written to, read from or refreshed. Fast speed offers faster perform-
ance while slow speed offers more stable performance. Settings: 3
Clocks, 2 Clocks.
Precharge Delay
The field specifies the idle cycles before precharging an idle bank.
Settings: 7 Clocks, 6 Clocks, 5 Clocks.
Burst Length
This setting allows you to set the size of Burst-Length for DRAM.
Bursting feature is a technique that DRAM itself predicts the
address of the next memory location to be accessed after the first
address is accessed. To use the feature, you need to define the
burst length, which is the actual length of burst plus the starting
address and allows internal address counter to properly generate
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