NI Digital System Development Board User Manual | © National Instruments | 13
connected to the processors as slaves via the AMBA interconnect, and contain readable/writable
control registers that are addressable in the processors’ memory space. The programmable logic
is also connected to the interconnect as a slave, and designs can implement multiple cores in the
FPGA fabric that each also contain addressable control registers. Furthermore, cores
implemented in the PL can trigger interrupts to the processors (connections not shown in
Figure 4) and perform DMA accesses to DDR3 memory.
There are many aspects of the Zynq AP SoC architecture that are beyond the scope of this
document. For a complete and thorough description, refer to the Zynq Technical Reference
Manual, available at www.xilinx.com. Table 3 depicts the external components connected to the
MIO pins of the DSDB.
Table 3. MIO Pinout
MIO 500 3.3 V Peripherals Peripherals Peripherals
Pin Pmod SPI Flash GPIO
0 JC9
1 CS
2 DQ0
3 DQ1
4 DQ2
5 DQ3
6 SCLK
7 LED15
8 SLCK FB
9 JC8
10 JC4
11 JC2
12 JC3
13 JC1
14 JC7
15 JF10
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