Figure 2.9 I/O signals (3 o f 5)
Pin
Name
Pin
Number
I/O
Description
DC Characteristics
Driver or Receiver Re
quirements o f each
Peripheral
RESET IN / c3 1
RESET IN / is an active low signal, which is
used to general system RESET. Internal is
a RC circu it and a Schm itt trigger inp ut. A
RESET is possible for example by a switch
to G R D .
Driver open collector
1 |_>40mA
Short protection
A B T R I/ c10 1
Address Bus Tri-state, active low signal.
Driver o nly open
collector l[_>8m A
RE AD Y D M A a10 0
Ready Signal from the memory controller
(X ACK), active high.
Receiver: l|_ <-1m A
I(-I<50uA
DIR /
c13 1
Direction o f the databus driver. Low signal
change to in put.
Driver open collector
I L> 8m A
TH O LD /
a14
1
Test H old. External request to set the Z80
in hold state.
Driver open collector
I [_>8m A
H LD A
c14
0
Hold Acknowledge. A response from Z80
processor. The Z80 processor is in hold
state, active high.
Receiver: l|_<-0.8m A
I h <40uA
PCLK/ a15 0
Processor-Clock: Inverse signal o f the pro
cessor lock (Z80) w ith a frequency of 4MHz.
Receiver: l|_< -0 .8m A
l|-)< 40u A
SYSTEM TECHNICAL MANUAL HARDWARE DESCRIPTION
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