Figure 2.9 I/O signals (4 o f 5)
Pin
Name
Pin
Number
I/O Description
DC Characteristics
Driver o r Receiver Re
quirements o f each
Peripheral
C L K 1/ c15 0 Clock o u tput 1 MHz.
I l < -0.8m A
Ih < 4 0 uA
TR A M D /
c16 I Test RAM-Disable. For external ROM or RAM
extension. Switching w ith the system RAM .
The RAM outpu t w ill be disabled. Used by the
Diagnostic module. The signal is active low.
Driver o n ly, open
collector l|_ >8m A
I N T/ c31 I INTERR UPT. Inte rru pt fo r Z80, active low. Driver o nly, open
collector I (_> 8mA
IN TA C K / a12 0
INTERRUP T ACKNO W LEDG E from the Z80
Processor, active low.
Receiver: li_< -1.2m A
I|-I<60uA
W A IT / a31
I W A IT / set the Z80, 8088, and DM A controller
in Wait-State (not ready), active low
Driver on ly, open
collector l|_ >8m A
DRQO c29
1
DMA-Request fo r Channel 0, active high Driver on ly Tristate
DRQ1
a 29 1
DMA Request fo r Channel 1, active high.
Asynchronous channel request inputs are used
by peripherals to request DM A service.
I h > -2mA
I i_>2mA
DACKO/ c30 0 DMA-Acknowledge Channel 0, active low.
Receiver: l[_<-0 .5m A
DACK1 / a 30 0 DM A-Acknowledge Channel 1, active low. These
lines indicate an active DM A channel.
IH < 2 0 uA
2 - 1 4
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