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NXP Semiconductors MC9S08SU16 - User Manual
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MC9S08SU16 Reference Manual
Supports: MC9S08SU16VFK MC9S08SU8VFK
Document Number: MC9S08SU16RM
Rev. 5, 4/2017
2
Table of Contents
Main Page
Default Chapter
3
Table of Contents
3
Chapter 1 About this Document
33
Overview
33
Purpose
33
Audience
33
Conventions
33
Numbering Systems
33
Typographic Notation
34
Special Terms
34
Chapter 2 Introduction
35
Module Functional Categories
35
S08L Core Modules
36
System Modules
36
Memories and Memory Interfaces
37
Clocks
37
Security and Integrity Modules
38
Analog Modules
38
Timer Modules
38
Communication Interfaces
39
Human-Machine Interfaces
39
MCU Block Diagram
40
Orderable Part Numbers
41
Chapter 3 Memory
43
Memory Map
43
Reset and Interrupt Vector Assignments
44
Register Addresses Assignments
46
Random-Access Memory (RAM)
51
Flash Memory
51
System Register File
52
Interrupts
53
Interrupt Stack Frame
54
Hardware Nested Interrupt
55
Chapter 4
57
Interrupt Priority Level Register
57
Interrupt Priority Level Comparator Set
57
Interrupt Priority Mask Update and Restore Mechanism
57
Integration and Application of the IPC
58
IPC Memory Map and Register Descriptions
59
IPC Status and Control Register (IPC_SC)
59
Interrupt Priority Mask Pseudo Stack Register (IPC_IPMPS)
60
Interrupt Level Setting Registers N (Ipc_Ilrsn)
61
Irq
61
Features
62
Configuration Options
63
Edge and Level Sensitivity
63
IRQ Memory Map and Register Descriptions
63
Interrupt Pin Request Status and Control Register (IRQ_SC)
63
Chapter 5 Clock Management
65
Clock Module
65
System Clock Distribution
65
Internal Clock Source (ICS)
67
20 Khz Low-Power Oscillator (LPO)
68
Peripheral Clock Gating
68
Chapter 6 Power Management
71
Introduction
71
Features
71
Run Mode
71
Wait Mode
72
Stop Mode
72
Active BDM Enabled in Stop Mode
72
Power Modes Behaviors
73
Bandgap Reference
74
Chapter 7 Signal Multiplexing and Signal Descriptions
75
Introduction
75
Port Control and Interrupt Module Features
75
Signal Multiplexing Constraints
75
Pinout
76
Signal Multiplexing and Pin Assignments
76
Signal Description Table
77
Pinout
81
Chapter 8 Port Control (PORT)
83
Introduction
83
Port Data and Data Direction
84
Internal Pullup/Pulldown Enable
84
Input Glitch Filter
85
Memory Map and Register Definition
86
Port a Data Register (PORT_PTAD)
86
Port B Data Register (PORT_PTBD)
87
Port C Data Register (PORT_PTCD)
87
Port a Direction Register (PORT_PTADD)
88
Port B Direction Register (PORT_PTBDD)
89
Port C Direction Register (PORT_PTCDD)
89
Port a Pullup Enable Register (PORT_PTAPE)
90
Port B Pullup/Pulldown Enable Register (PORT_PTBPE)
91
Port C Pullup Enable Register (PORT_PTCPE)
91
Port B High Drive Strength Selection Register (PORT_PTBHD)
92
Port Clock Division Register (PORT_FCLKDIV)
92
Port Filter Register 0 (PORT_IOFLT0)
93
Port Filter Register 1 (PORT_IOFLT1)
94
Port Filter Register 2 (PORT_IOFLT2)
95
Chapter 9 System Integration Module (SIM)
97
Chip Specific Windowed COP
97
System Device Identification (SDID)
98
Universally Unique Identification (UUID)
98
Reset and System Initialization
98
Computer Operating Properly (COP) Watchdog
99
System Options
100
BKGD Pin
100
Reset_B Pin Enable
101
System Interconnection
101
Inter Module Crossbar Switch (XBAR)
101
Module to Module Interconnects
103
Memory Map and Register Definition
104
System Reset Status Register (SIM_SRS)
105
System Background Debug Force Reset Register (SIM_SBDFR)
107
System Device Identification Register: High (SIM_SDIDH)
107
System Device Identification Register: Low (SIM_SDIDL)
108
System Options Register 1 (SIM_SOPT1)
108
System Options Register 2 (SIM_SOPT2)
110
System Port a Pin Multiplexing Control Register: Low (SIM_MUXPTAL)
111
System Port a Pin Multiplexing Control Register: High (SIM_MUXPTAH)
112
System Port B Pin Multiplexing Control Register: Low (SIM_MUXPTBL)
113
System Port B Pin Multiplexing Control Register: High (SIM_MUXPTBH)
114
System Port C Pin Multiplexing Control Register: Low (SIM_MUXPTCL)
116
System Clock Gating Control 1 Register (SIM_SCGC1)
116
System Clock Gating Control 2 Register (SIM_SCGC2)
117
System Clock Gating Control 3 Register (SIM_SCGC3)
119
System Clock Divider Register (SIM_SCDIV)
120
System por Register (Sim_Porregn)
121
Illegal Address Register: High (SIM_ILLAH)
122
Illegal Address Register: Low (SIM_ILLAL)
122
Universally Unique Identifier Register 0 (SIM_UUID0)
123
Universally Unique Identifier Register 1 (SIM_UUID1)
123
Universally Unique Identifier Register 2 (SIM_UUID2)
124
Universally Unique Identifier Register 3 (SIM_UUID3)
124
Universally Unique Identifier Register 4 (SIM_UUID4)
125
Universally Unique Identifier Register 5 (SIM_UUID5)
125
Universally Unique Identifier Register 6 (SIM_UUID6)
126
Universally Unique Identifier Register 7 (SIM_UUID7)
126
Chapter 10 Central Processor Unit
127
Introduction
127
Features
127
Programmer's Model and CPU Registers
128
Accumulator (A)
128
Index Register (H:X)
129
Stack Pointer (SP)
129
Program Counter (PC)
130
Condition Code Register (CCR)
130
Addressing Modes
131
Inherent Addressing Mode (INH)
132
Relative Addressing Mode (REL)
132
Immediate Addressing Mode (IMM)
132
Direct Addressing Mode (DIR)
133
Extended Addressing Mode (EXT)
133
Indexed Addressing Mode
134
Indexed, 8-Bit Offset (IX1)
134
Indexed, no Offset (IX)
134
Indexed, no Offset with Post Increment (IX+)
134
Indexed, 16-Bit Offset (IX2)
135
Indexed, 8-Bit Offset with Post Increment (IX1+)
135
SP-Relative, 8-Bit Offset (SP1)
135
SP-Relative, 16-Bit Offset (SP2)
136
Memory to Memory Addressing Mode
136
Direct to Direct
136
Immediate to Direct
136
Direct to Indexed, Post-Increment
137
Indexed to Direct, Post Increment
137
Operation Modes
137
Stop Mode
137
Wait Mode
138
Background Mode
138
Security Mode
139
HCS08 V6 Opcodes
141
Special Operations
141
Reset Sequence
141
Interrupt Sequence
141
Instruction Set Summary
142
Chapter 11 Flash Memory Module (FTMRH)
155
Introduction
155
Feature
155
Flash Memory Features
155
Other Flash Module Features
156
Functional Description
156
Modes of Operation
156
Stop Mode
156
Wait Mode
156
Flash Block Read Access
156
Flash Memory Map
157
Flash Initialization after System Reset
157
Flash Command Operations
157
Writing the FCLKDIV Register
158
Command Write Sequence
160
Flash Interrupts
162
Description of Flash Interrupt Operation
162
Protection
163
Security
165
Unsecuring the MCU Using Backdoor Key Access
166
Mode and Security Effects on Flash Command Availability
167
Unsecuring the MCU Using BDM
167
Flash Commands
167
Flash Command Summary
168
Erase Verify All Blocks Command
169
Erase Verify Flash Section Command
170
Read Once Command
171
Program Flash Command
172
Program Once Command
173
Erase All Blocks Command
174
Erase Flash Block Command
175
Unsecure Flash Command
176
Verify Backdoor Access Key Command
177
Set User Margin Level Command
178
Set Factory Margin Level Command
179
Memory Map and Register Definition
180
Flash Clock Divider Register (FTMRH_FCLKDIV)
181
Flash Security Register (FTMRH_FSEC)
182
Flash CCOB Index Register (FTMRH_FCCOBIX)
183
Flash Status Register (FTMRH_FSTAT)
184
Flash Protection Register (FTMRH_FPROT)
185
Flash Common Command Object Register:high (FTMRH_FCCOBHI)
186
Flash Common Command Object Register: Low (FTMRH_FCCOBLO)
187
Introduction
189
Block Diagram
190
FLL Engaged External (FEE)
190
FLL Engaged Internal (FEI)
190
FLL Bypassed External (FBE)
191
FLL Bypassed External Low Power (FBELP)
191
FLL Bypassed Internal (FBI)
191
FLL Bypassed Internal Low Power (FBILP)
191
Stop (STOP)
191
External Signal Description
191
Register Definition
192
ICS Control Register 1 (ICS_C1)
192
ICS Control Register 2 (ICS_C2)
193
ICS Control Register 3 (ICS_C3)
194
ICS Control Register 4 (ICS_C4)
195
ICS Status Register (ICS_S)
196
Functional Description
197
Operational Modes
197
FLL Engaged Internal (FEI)
197
FLL Bypassed Internal (FBI)
198
FLL Bypassed Internal Low Power (FBILP)
198
FLL Engaged External (FEE)
198
FLL Bypassed External (FBE)
199
FLL Bypassed External Low Power (FBELP)
199
Stop
199
Mode Switching
200
Bus Frequency Divider
200
Low-Power Field Usage
200
Internal Reference Clock
200
Fixed Frequency Clock
201
FLL Lock and Clock Monitor
201
FLL Clock Lock
201
External Reference Clock Monitor
202
Initialization/Application Information
202
Initializing FEI Mode
202
Initializing FBI Mode
202
Initializing FEE Mode
203
Initializing FBE Mode
203
Chapter 13 Modulo Timer (MTIM)
205
Chip Specific Modulo Timer
205
Introduction
205
Features
206
Block Diagram
206
Modes of Operation
207
MTIM16 in Stop Modes
207
MTIM16 in Wait Mode
207
MTIM16 in Active Background Mode
208
External Signal Description
208
TCLK - External Clock Source Input into MTIM16
208
Memory Map and Register Descriptions
209
MTIM16 Status and Control Register (MTIM_SC)
209
MTIM16 Clock Configuration Register (MTIM_CLK)
210
MTIM16 Counter Register High (MTIM_CNTH)
211
MTIM16 Counter Register Low (MTIM_CNTL)
212
MTIM16 Modulo Register High (MTIM_MODH)
213
MTIM16 Modulo Register Low (MTIM_MODL)
214
Functional Description
214
MTIM16 Operation Example
216
Power Management Controller (PMC)
217
Chip Specific Power Management Controller
217
Introduction
217
Features
218
Overview
218
Modes of Operation
219
Reduced Performance Mode
219
Full Performance Mode
220
External Signal Description
220
VDD
220
VDDX
220
Vrefh
220
Vddf
221
Vdd1.8
221
Memory Map and Register Definition
221
Control Register (PMC_CTRL)
222
Reset Flags Register (PMC_RST)
223
Temperature Control and Status Register (PMC_TPCTRLSTAT)
223
Temperature Offset Step Trim Register (PMC_TPTM)
224
RC Oscillator Offset Step Trim Register (PMC_RC20KTRM)
225
Low Voltage Control and Status Register 1 (System 5 V) (PMC_LVCTLSTAT1)
226
Low Voltage Control and Status Register 2 (VREFH ) (PMC_LVCTLSTAT2)
227
VREFH Configuration Register (PMC_VREFHCFG)
227
VREFH Low Voltage Warning (LVW) Configuration Register (PMC_VREFHLVW)
228
Status Register (PMC_STAT)
228
Functional Description
229
Voltage Regulators
229
Vregvddf
229
Vregvddx
229
Vregvdd
230
Vregvrefh
230
Power-On Reset
230
Low Voltage Reset (LVR)
230
LVR in Low Power Mode
231
Low Voltage Warning (LVW)
231
LVW in Low Power Mode
231
LVW on VDDX/VDDA
231
LVW on VREFH
231
High-Accuracy Reference Voltage
232
Temperature Sensor
232
High Temperature Warning
232
Low-Power RC Oscillator
233
Application Information
233
Chapter 15 Keyboard Interrupts (KBI)
235
Chip Specific KBI Information
235
Introduction
235
Features
235
Modes of Operation
235
KBI in Stop Modes
236
KBI in Wait Mode
236
Block Diagram
236
External Signals Description
237
Register Definition
237
Memory Map and Registers
237
KBI Status and Control Register (KBI_SC)
238
KBI Pin Enable Register (KBI_PE)
239
KBI Edge Select Register (KBI_ES)
239
Functional Description
240
KBI Pullup Resistor
241
Chapter 16 Chip Specific Cyclic Redundancy Check (CRC)
243
Chapter 28 Features
244
Run Mode
245
CRC Data Register: High 0 (CRC_DH0)
246
CRC Data Register: Low 1 (CRC_DL1)
247
CRC Polynomial Register: High 1 (CRC_PH1)
248
CRC Polynomial Register: High 0 (CRC_PH0)
249
CRC Polynomial Register: Low 0 (CRC_PL0)
250
Functional Description
251
CRC Calculations
252
Transpose Feature
253
CRC Result Complement
254
Chip-Specific ADC Information
255
Chapter 17
256
ADC Channel Assignments
256
ADC Analog Supply and Reference Connections
257
Hardware Trigger
258
Introduction
259
Block Diagram
260
Analog Channel Inputs (Adx)
262
Status and Control Register 2 (Adcx_Sc2)
264
Status and Control Register 3 (Adcx_Sc3)
265
Status and Control Register 4 (Adcx_Sc4)
266
Conversion Result High Register (Adcx_Rh)
267
Conversion Result Low Register (Adcx_Rl)
268
Compare Value High Register (Adcx_Cvh)
269
Functional Description
270
Hardware Trigger
271
Completing Conversions
272
Power Control
273
Automatic Compare Function
274
FIFO Operation
275
MCU Wait Mode Operation
279
Initialization Information
280
Pseudo-Code Example
281
Pseudo-Code Example
282
Application Information
283
Analog Input Pins
284
Sources of Error
285
Code Width and Quantization Error
286
Linearity Errors
287
Code Jitter, Non-Monotonicity, and Missing Codes
288
Chapter 18
289
CMP Configuration Information
289
ACMP in Stop Mode
290
CMP Features
291
ANMUX Key Features
292
CMP Block Diagram
293
Memory Map/Register Definitions
295
CMP Control Register 1 (CMP_CR1)
296
CMP Filter Period Register (CMP_FPR)
297
CMP Status and Control Register (CMP_SCR)
298
DAC Control Register (CMP_DACCR)
299
MUX Control Register (CMP_MUXCR)
300
MUX Pin Enable Register (CMP_MUXPE)
301
CMP Functional Modes
302
Disabled Mode (# 1)
303
Sampled, Non-Filtered Mode (#S 3A & 3B)
304
Sampled, Filtered Mode (#S 4A & 4B)
306
Windowed Mode (#S 5A & 5B)
308
Windowed/Resampled Mode (# 6)
310
Windowed/Filtered Mode (#7)
311
Stop Mode Operation
312
Low Pass Filter
313
Latency Issues
314
CMP Interrupts
315
DAC Functional Description
316
Chapter 19
317
Chip Specific Flextimer Module
317
Introduction
318
Modes of Operation
319
Signal Description
320
EXTCLK — FTM External Clock
321
Status and Control (Ftmx_Sc)
322
Counter High (Ftmx_Cnth)
323
Counter Low (Ftmx_Cntl)
324
Modulo Low (Ftmx_Modl)
325
Channel Status and Control (Ftmx_Cnsc)
326
Channel Value High (Ftmx_Cnvh)
327
Channel Value Low (Ftmx_Cnvl)
328
Functional Description
329
Prescaler
330
Up Counting
331
Free Running Counter
332
Output Compare Mode
333
Edge-Aligned PWM (EPWM) Mode
335
Center-Aligned PWM (CPWM) Mode
336
Update of the Registers with Write Buffers
338
Cnvh:l Registers
339
FTM Interrupts
341
Chapter 20 Chip Specific Pules Width Timer
343
Introduction
344
Chapter 24
345
Block Diagram
345
PWTIN[3:0] — Pulse Width Timer Capture Inputs
346
Pulse Width Timer Control and Status Register (Pwtx_Cs)
347
Pulse Width Timer Control Register (Pwtx_Cr)
348
Pulse Width Timer Positive Pulse Width Register: High (Pwtx_Pph)
349
Pulse Width Timer Positive Pulse Width Register: Loq (Pwtx_Ppl)
350
Pulse Width Timer Negative Pulse Width Register: Low (Pwtx_Npl)
351
Functional Description
352
Reset Overview
356
Interrupts
357
Application Examples
358
Initialization/Application Information
359
Chapter 21
361
Chip Specific Inter-Integrated Circuit
361
Features
362
Block Diagram
363
I2C Signal Descriptions
364
I2C Address Register 1 (I2C_A1)
365
I2C Control Register 1 (I2C_C1)
366
I2C Status Register (I2C_S)
368
I2C Data I/O Register (I2C_D)
369
I2C Control Register 2 (I2C_C2)
370
I2C Stop Control and Status Register (I2C_SCS)
371
I2C Range Address Register (I2C_RA)
372
I2C Smbus Control and Status Register (I2C_SMB)
373
I2C Address Register 2 (I2C_A2)
374
I2C SCL Low Timeout Register High (I2C_SLTH)
375
I2C Status Register 2 (I2C_S2)
376
I2C Protocol
377
Slave Address Transmission
378
STOP Signal
379
Clock Synchronization
380
Clock Stretching
381
Bit Address
382
Master-Receiver Addresses a Slave-Transmitter
383
System Management Bus Specification
384
FAST ACK and NACK
386
Resets
387
Byte Transfer Interrupt
388
Timeout Interrupt in Smbus
389
Double Buffering Mode
390
Initialization/Application Information
391
Chapter 22
395
Chip Specific Serial Communications Interface
395
Introduction
396
Modes of Operation
397
SCI Signal Descriptions
399
SCI Baud Rate Register: High (Scix_Bdh)
400
SCI Baud Rate Register: Low (Scix_Bdl)
401
SCI Control Register 2 (Scix_C2)
403
SCI Status Register 1 (Scix_S1)
404
SCI Status Register 2 (Scix_S2)
406
SCI Control Register 3 (Scix_C3)
407
SCI Data Register (Scix_D)
409
Baud Rate Generation
410
Send Break and Queued Idle
411
Receiver Functional Description
412
Data Sampling Technique
413
Receiver Wake-Up Operation
414
Interrupts and Status Flags
415
Baud Rate Tolerance
416
Slow Data Tolerance
417
Fast Data Tolerance
418
Additional SCI Functions
419
Loop Mode
420
Chapter 23
421
Chip Specific Programmable Delay Block
421
Introduction
422
Mode of Operation
423
Continuous Count Mode
424
Memory Map and Register Descriptions
425
PDB Control Register 1 (PDB_CTRL1)
426
PDB0 Comparison Low Register (PDB_CMPL0)
427
PDB0 Comparison High Register (PDB_CMPH0)
428
PDB1 Comparison Low Register (PDB_CMPL1)
429
PDB1 Counter High/Low (PDB_CNT1)
430
Introduction
431
Memory Map and Register Descriptions
432
External Mux Selection Register (XBAR_EXTMUX)
433
XBAR Selection Register (Xbar_Seln)
434
Chapter 25 Chip Specific GDU Information
435
Features
436
Modes of Operation
437
Memory Map and Register Definition
438
PHCMP0 Control Register 0 (GDU_PHCMP0CR0)
439
PHCMP0 Filter Period Register (GDU_PHCMP0FPR)
441
PHCMP1 Control Register 0 (GDU_PHCMP1CR0)
442
PHCMP1 Control Register 1 (GDU_PHCMP1CR1)
443
PHCMP1 Filter Period Register (GDU_PHCMP1FPR)
444
PHCMP1 Status and Control Register (GDU_PHCMP1SCR)
445
PHCMP2 Control Register 0 (GDU_PHCMP2CR0)
446
PHCMP2 Filter Period Register (GDU_PHCMP2FPR)
448
Clamp Control Register (GDU_CLMPCTRL)
449
I/O Control Register (GDU_IOCTRL)
450
Virtual Network Phase Detection Control (GDU_PHASECTRL)
451
Current Sensor and Overcurrent Protection Control Register (GDU_CURCTRL)
452
LIMIT0 CMP Control Register 1 (GDU_LIMIT0CR1)
453
LIMIT0 CMP Filter Period Register (GDU_LIMIT0FPR)
454
LIMIT0 CMP Status and Control Register (GDU_LIMIT0SCR)
455
LIMIT0 DAC Control Register (GDU_LIMIT0DACCR)
456
LIMIT1 CMP Control Register 1 (GDU_LIMIT1CR1)
457
LIMIT1 CMP Filter Period Register (GDU_LIMIT1FPR)
458
LIMIT1 CMP Status and Control Register (GDU_LIMIT1SCR)
459
LIMIT1 DAC Control Register (GDU_LIMIT1DACCR)
460
LIMIT CMP BIAS Register (GDU_SIGBIAS)
461
Phase Detection Function Descriptions
462
Opamp Function Descriptions
463
Opamp Descriptions
464
Predrive Descriptions
465
GCMP Diagram
466
GCMP Functional Modes
468
Power Modes
477
Startup and Operation
478
GCMP Interrupts
480
Chip Specific Pulse Width Modulator
481
MC9S08SU16 Reference Manual, Rev. 5, 4/2017 NXP Semiconductors
482
Modes of Operation
483
Functional Description
485
Alignment and Compare Output Polarity
486
Period
487
Independent or Complementary Channel Operation
489
Deadtime Generators
491
Asymmetric PWM Output
493
PWM Output Polarity
494
Generator Loading
497
Reload Flag
498
Initialization
500
Fault Protection
501
Fault Pin Filter
502
Automatic Fault Clearing
503
Memory Map and Register Descriptions
504
PWM Control Register: Low (PWM_CTRLL)
506
PWM Control Register: High (PWM_CTRLH)
507
PWM Fault Control Register: Low (PWM_FCTRLL)
508
PWM Fault Control Register: High (PWM_FCTRLH)
510
PWM Fault Status Acknowledge Register: High (PWM_FLTACKH)
511
PWM Output Control Register: Low (PWM_OUTL)
513
PWM Output Control Register: High (PWM_OUTH)
514
PWM Counter Register: High (PWM_CNTRH)
515
PWM Counter Register: High (PWM_CMODH)
516
PWM Value Register: High (Pwm_Valnh)
517
PWM Deadtime Register: Low (Pwm_Dtimnl)
518
PWM Disable Mapping Registers 1: Low (PWM_DMAP1L)
519
PWM Disable Mapping Registers 1: High (PWM_DMAP1H)
520
PWM Configure Register: High (PWM_CNFGH)
521
PWM Channel Control Register: Low (PWM_CCTRLL)
522
PWM Channel Control Register: High (PWM_CCTRLH)
524
PWM Compare Invert Register: High (PWM_CINVH)
525
Resets
526
Interrupts
527
Background Debug Controller (BDC)
530
BKGD Pin Description
531
Communication Details
532
BDC Commands
534
BDC Hardware Breakpoint
537
Comparators a and B
538
Bus Capture Information and FIFO Operation
539
Change-Of-Flow Information
540
Trigger Modes
541
Hardware Breakpoints
542
Memory Map and Register Description
543
BDC Breakpoint Match Register: High (BDC_BKPTH)
545
BDC Breakpoint Register: Low (BDC_BKPTL)
546
Introduction
549
Modes of Operation
550
Signal Description
551
Debug Comparator a High Register (DBG_CAH)
552
Debug Comparator a Low Register (DBG_CAL)
553
Debug Comparator B High Register (DBG_CBH)
554
Debug Comparator C High Register (DBG_CCH)
555
Debug Comparator C Low Register (DBG_CCL)
556
Debug FIFO Low Register (DBG_FL)
557
Debug Comparator a Extension Register (DBG_CAX)
558
Debug Comparator B Extension Register (DBG_CBX)
559
Debug Comparator C Extension Register (DBG_CCX)
560
Debug FIFO Extended Information Register (DBG_FX)
561
Debug Trigger Register (DBG_T)
562
Debug Status Register (DBG_S)
564
Debug Count Status Register (DBG_CNT)
565
Functional Description
566
Breakpoints
567
Trigger Selection
568
Begin- and End-Trigger
569
Trigger Modes
570
Fifo
572
Storing Data in FIFO
573
Resets
575
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NXP Semiconductors MC9S08SU16 Specifications
General
Brand
NXP Semiconductors
Model
MC9S08SU16
Category
Microcontrollers
Language
English
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