NXP Semiconductors LPC1768

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UM10360

LPC176x/5x User manual

Rev. 3 — 20 December 2013 User manual

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Info Content

Keywords LPC1769, LPC1768, LPC1767, LPC1766, LPC1765, LPC1764, LPC1763,

LPC1759, LPC1758, LPC1756, LPC1754, LPC1752, LPC1751, ARM, ARM

Cortex-M3, 32-bit, USB, Ethernet, CAN, I2S, Microcontroller

Abstract LPC176x/5x user manual

Main Page

Chapter 1: Lpc176X/5X Introductory Information4
Introduction4
Features5
Applications7
Ordering Information8
- Part Options Summary8
Simplified Block Diagram9
Chapter 35 : Supplementary Information10
Architectural Overview10
ARM Cortex-M3 Processor10
- Cortex-M3 Configuration Options10
  - System Options10
  - Debug Related Options11
On-Chip Flash Memory System11
On-Chip Static RAM11
Block Diagram12
Chapter 2: Lpc176X/5X Memory Map13
Memory Map and Peripheral Addressing13
Memory Maps13
APB Peripheral Addresses15
Memory Re-Mapping16
- Boot ROM Re-Mapping16
AHB Arbitration16
Bus Fault Exceptions16
Chapter 3: Lpc176X/5X System Control18
Introduction18
Pin Description18
Register Description19
Reset19
- Reset Source Identification Register (RSID - 0X400F C180)22
Brown-Out Detection23
External Interrupt Inputs24
- Register Description25
Other System Controls and Status Flags29
- System Controls and Status Register (SCS - 0X400F C1A0)29
Chapter 4: Lpc176X/5X Clocking and Power Control30
Summary of Clocking and Power Control Functions30
Register Description31
Oscillators32
- Internal RC Oscillator32
- Main Oscillator32
- RTC Oscillator34
Clock Source Selection Multiplexer35
- Clock Source Select Register (CLKSRCSEL - 0X400F C10C)35
PLL0 (Phase Locked Loop 0)36
- PLL0 Operation36
- PLL0 and Startup/Boot Code Interaction36
- PLL0 Register Description37
- PLL0 Control Register (PLL0CON - 0X400F C080)37
- PLL0 Configuration Register (PLL0CFG - 0X400F C084)38
- PLL0 Status Register (PLL0STAT - 0X400F C088)39
- PLL0 Interrupt: PLOCK040
- PLL0 Modes40
- PLL0 Feed Register (PLL0FEED - 0X400F C08C)41
- PLL0 and Power-Down Mode41
- PLL0 Frequency Calculation41
- Procedure for Determining PLL0 Settings43
- Examples of PLL0 Settings44
- PLL0 Setup Sequence47
PLL1 (Phase Locked Loop 1)48
- PLL1 Register Description48
- PLL1 Control Register48
  - C0A0)49
- PLL1 Configuration Register (PLL1CFG - 0X400F C0A4)50
- PLL1 Status Register (PLL1STAT - 0X400F C0A8)50
- PLL1 Modes51
- PLL1 Interrupt: PLOCK151
- PLL1 Feed Register52
  - C0Ac)52
- PLL1 and Power-Down Mode52
- PLL1 Frequency Calculation53
- Procedure for Determining PLL1 Settings53
Clock Dividers55
- CPU Clock Configuration Register (CCLKCFG - 0X400F C104)55
- USB Clock Configuration Register (USBCLKCFG - 0X400F C108)56
- Peripheral Clock Selection Registers 0 and 157
Power Control59
- Sleep Mode59
  - Deep Sleep Mode59
- Power-Down Mode60
- Deep Power-Down Mode61
- Peripheral Power Control61
- Register Description61
- Power Mode Control Register (PCON - 0X400F C0C0)62
- Encoding of Reduced Power Modes63
  - Wake-Up from Reduced Power Modes63
- Power Control for Peripherals Register (PCONP - 0X400F C0C4)63
- Power Control Usage Notes65
- Power Domains65
Wake-Up Timer66
External Clock Output Pin67
- Clock Output Configuration Register67
Chapter 5: Lpc176X/5X Flash Accelerator69
Introduction69
Flash Accelerator Blocks69
- Flash Memory Bank69
- Flash Programming Issues70
Register Description70
Flash Accelerator Configuration Register71
Operation71
Chapter 6: Lpc176X/5X Nested Vectored Interrupt Controller (NVIC)73
Features73
Description73
Interrupt Sources73
Vector Table Remapping76
- Examples76
Register Description77
- Interrupt Set-Enable Register 0 Register (ISER0 - 0Xe000 E100)78
- Interrupt Set-Enable Register 1 Register (ISER1 - 0Xe000 E104)79
- Interrupt Clear-Enable Register 0 (ICER0 - 0Xe000 E180)80
- Interrupt Clear-Enable Register 1 Register (ICER1 - 0Xe000 E184)81
- Interrupt Set-Pending Register 0 Register (ISPR0 - 0Xe000 E200)82
- Interrupt Set-Pending Register 1 Register (ISPR1 - 0Xe000 E204)83
  - (ICPR0 - 0Xe000 E280)84
- Interrupt Clear-Pending Register 1 Register85
  - (ICPR1 - 0Xe000 E284)85
- Interrupt Active Bit Register 0 (IABR0 - 0Xe000 E300)86
- Interrupt Active Bit Register 1 (IABR1 - 0Xe000 E304)87
- Interrupt Priority Register 0 (IPR0 - 0Xe000 E400)88
- Interrupt Priority Register 1 (IPR1 - 0Xe000 E404)88
- Interrupt Priority Register 2 (IPR2 - 0Xe000 E408)88
- Interrupt Priority Register 3 (IPR3 - 0Xe000 E40C)89
- Interrupt Priority Register 4 (IPR4 - 0Xe000 E410)89
- Interrupt Priority Register 5 (IPR5 - 0Xe000 E414)89
- Interrupt Priority Register 6 (IPR6 - 0Xe000 E418)90
- Interrupt Priority Register 7 (IPR7 - 0Xe000 E41C)90
- Interrupt Priority Register 8 (IPR8 - 0Xe000 E420)90
- Software Trigger Interrupt Register (STIR - 0Xe000 EF00)91
Chapter 7: Lpc176X/5X Pin Configuration92
Lpc176X/5X Pin Configuration92
Lpc176X/5X Pin Description95
Chapter 8: Lpc176X/5X Pin Connect Block105
How to Read this Chapter105
Description105
Pin Function Select Register Values105
- Multiple Connections106
Pin Mode Select Register Values106
- Function of PINMODE in Open Drain Mode107
Register Description108
- Pin Control Module Register Reset Values108
- Pin Function Select Register 0 (PINSEL0 - 0X4002 C000)109
- Pin Function Select Register 1 (PINSEL1 - 0X4002 C004)109
- Pin Function Select Register 2 (PINSEL2 - 0X4002 C008)110
- Pin Function Select Register 3 (PINSEL3 - 0X4002 C00C)110
- Pin Function Select Register 4 (PINSEL4 - 0X4002 C010)111
- Pin Function Select Register 7 (PINSEL7 - 0X4002 C01C)112
- Pin Function Select Register 9 (PINSEL9 - 0X4002 C024)112
- Pin Function Select Register 10 (PINSEL10 - 0X4002 C028)112
  - Pin Mode Select Register 0 (PINMODE0 - 0X4002 C040)113
- Pin Mode Select Register 1 (PINMODE1 - 0X4002 C044)113
- Pin Mode Select Register 2 (PINMODE2 - 0X4002 C048)114
- Pin Mode Select Register 3 (PINMODE3 - 0X4002 C04C)114
- Pin Mode Select Register 4 (PINMODE4 - 0X4002 C050)115
- Pin Mode Select Register 7 (PINMODE7 - 0X4002 C05C)116
- Pin Mode Select Register 9 (PINMODE9 - 0X4002 C064)116
- Open Drain Pin Mode Select Register 0 (PINMODE_OD0 - 0X4002 C068)116
- Open Drain Pin Mode Select Register117
  - (PINMODE_OD1 - 0X4002 C06C)117
- Open Drain Pin Mode Select Register 2 (PINMODE_OD2 - 0X4002 C070)118
- Open Drain Pin Mode Select Register 3 (PINMODE_OD3 - 0X4002 C074)119
- Open Drain Pin Mode Select Register 4 (PINMODE_OD4 - 0X4002 C078)119
- C Pin Configuration Register (I2CPADCFG - 0X4002 C07C)120
Chapter 9 : Lpc176X/5X General Purpose Input/Output (GPIO)121
Basic Configuration121
Features121
- Digital I/O Ports121
- Interrupt Generating Digital Ports121
Applications122
Pin Description122
Register Description123
- GPIO Port Direction Register Fioxdir (FIO0DIR to FIO4DIR- 0X2009 C000 to 0X2009 C080)124
- GPIO Port Output Set Register Fioxset (FIO0SET to FIO4SET - 0X2009 C018 to 0X2009 C098)125
- GPIO Port Output Clear Register Fioxclr (FIO0CLR to FIO4CLR- 0X2009 C01C to 0X2009 C09C)127
- GPIO Port Pin Value Register Fioxpin (FIO0PIN to FIO4PIN- 0X2009 C014 to 0X2009 C094)128
- Fast GPIO Port Mask Register Fioxmask (FIO0MASK to FIO4MASK - 0X2009 C010 to 0X2009 C090)130
- GPIO Interrupt Registers132
- GPIO Overall Interrupt Status Register (Iointstatus - 0X4002 8080)132
- GPIO Interrupt Enable for Port 0 Rising Edge (Io0Intenr - 0X4002 8090)132
- GPIO Interrupt Enable for Port 2 Rising Edge (Io2Intenr - 0X4002 80B0)133
- GPIO Interrupt Enable for Port 0 Falling Edge (Io0Intenf - 0X4002 8094)134
- GPIO Interrupt Enable for Port 2 Falling Edge (Io2Intenf - 0X4002 80B4)135
- GPIO Interrupt Status for Port 0 Rising Edge Interrupt (Io0Intstatr - 0X4002 8084)136
- GPIO Interrupt Status for Port 2 Rising Edge Interrupt (Io2Intstatr - 0X4002 80A4)137
- GPIO Interrupt Status for Port 0 Falling Edge Interrupt (Io0Intstatf - 0X4002 8088)137
- GPIO Interrupt Status for Port 2 Falling Edge Interrupt (Io2Intstatf - 0X4002 80A8)138
- GPIO Interrupt Clear Register for Port 0 (Io0Intclr - 0X4002 808C)139
- GPIO Interrupt Clear Register for Port 2 (Io2Intclr - 0X4002 80AC)140
GPIO Usage Notes141
- Example: an Instantaneous Output of 0S and 1S on a GPIO Port141
- Writing to FIOSET/FIOCLR Vs. FIOPIN141
Chapter 10: Lpc176X/5X Ethernet142
Basic Configuration142
Introduction142
Features143
Architecture and Operation144
DMA Engine Functions145
Overview of DMA Operation145
Ethernet Packet146
Overview147
- Partitioning147
- Example PHY Devices148
Pin Description148
Registers and Software Interface149
- Register Map149
Ethernet MAC Register Definitions151
- MAC Configuration Register 1 (MAC1 - 0X5000 0000)151
- MAC Configuration Register 2 (MAC2 - 0X5000 0004)151
- Back-To-Back Inter-Packet-Gap Register (IPGT - 0X5000 0008)153
- Non Back-To-Back Inter-Packet-Gap Register (IPGR - 0X5000 000C)153
- Collision Window / Retry Register (CLRT - 0X5000 0010)154
- Maximum Frame Register (MAXF - 0X5000 0014)154
- PHY Support Register (SUPP - 0X5000 0018)154
- Test Register (TEST - 0X5000 001C)154
- MII Mgmt Configuration Register (MCFG - 0X5000 0020)155
- MII Mgmt Command Register156
  - 0X5000 0024)156
- MII Mgmt Address Register156
  - 0X5000 0028)156
- MII Mgmt Write Data Register156
  - 0X5000 002C)156
- MII Mgmt Read Data Register157
  - 0X5000 0030)157
- MII Mgmt Indicators Register157
- 0X5000 0034)157
  - Station Address 0 Register158
- Station Address 1 Register158
- Station Address 2 Register158
Control Register Definitions159
- Command Register (Command - 0X5000 0100)159
- Status Register (Status - 0X5000 0104)159
- Receive Descriptor Base Address Register (Rxdescriptor - 0X5000 0108)160
- Receive Status Base Address Register (Rxstatus - 0X5000 010C)160
- Receive Number of Descriptors Register (Rxdescriptor - 0X5000 0110)160
- Receive Produce Index Register (Rxproduceindex - 0X5000 0114)161
- Receive Consume Index Register (Rxconsumeindex - 0X5000 0118)161
- Transmit Descriptor Base Address Register (Txdescriptor - 0X5000 011C)162
- Transmit Status Base Address Register (Txstatus - 0X5000 0120)162
- Transmit Number of Descriptors Register (Txdescriptornumber - 0X5000 0124)162
- Transmit Produce Index Register (Txproduceindex - 0X5000 0128)163
- Transmit Consume Index Register (Txconsumeindex - 0X5000 012C)163
- Transmit Status Vector 0 Register163
  - 0X5000 0158)163
- Transmit Status Vector 1 Register164
  - 0X5000 015C)164
- Receive Status Vector Register165
  - 0X5000 0160)165
- Flow Control Counter Register (Flowcontrolcounter - 0X5000 0170)166
- Flow Control Status Register166
  - 0X5000 0174)166
Receive Filter Register Definitions167
- Receive Filter Control Register167
  - 0X5000 0200)167
- Receive Filter Wol Status Register167
- Receive Filter Wol Clear Register (Rxfilterwolclear - 0X5000 0208)168
- Hash Filter Table Lsbs Register (Hashfilterl - 0X5000 0210)168
- Hash Filter Table Msbs Register169
  - 0X5000 0214)169
Module Control Register Definitions169
- Interrupt Status Register169
  - 0X5000 0FE0)169
- Interrupt Enable Register170
  - 0X5000 0FE4)170
  - 0Fe8)170
- Interrupt Set Register (Intset - 0X5000 0FEC)171
- Power-Down Register172
  - 0X5000 0FF4)172
Descriptor and Status Formats173
- Receive Descriptors and Statuses173
- Transmit Descriptors and Statuses176
Ethernet Block Functional Description178
- Overview178
- AHB Interface179
Interrupts179
- Direct Memory Access (DMA)179
- Initialization182
- Transmit Process183
- Receive Process189
- Transmission Retry195
- Status Hash CRC Calculations195
- Duplex Modes196
- IEE 802.3/Clause 31 Flow Control196
- Half-Duplex Mode Backpressure198
- Receive Filtering199
- Power Management201
- Wake-Up on LAN201
- Enabling and Disabling Receive and Transmit203
- Transmission Padding and CRC205
- Huge Frames and Frame Length Checking206
- Statistics Counters206
- MAC Status Vectors206
- Reset207
- Ethernet Errors208
AHB Bandwidth209
- DMA Access209
- Types of CPU Access210
- Overall Bandwidth210
CRC Calculation212
Chapter 11 : Lpc176X/5X USB Device Controller214
How to Read this Chapter214
Basic Configuration214
Introduction214
Features215
Fixed Endpoint Configuration215
Functional Description216
- Analog Transceiver217
- Serial Interface Engine (SIE)217
- Endpoint RAM (EP_RAM)217
- EP_RAM Access Control217
- DMA Engine and Bus Master Interface218
- Register Interface218
- Softconnect218
- Goodlink218
Operational Overview218
Pin Description219
Clocking and Power Management219
- Power Requirements219
- Clocks219
- Power Management Support220
- Remote Wake-Up221
Register Description221
- Clock Control Registers222
- USB Clock Control Register222
  - 0X5000 CFF4)222
- USB Clock Status Register223
  - Cff8)223
- Device Interrupt Registers223
- USB Interrupt Status Register223
  - 0X5000 C1C0)223
- USB Device Interrupt Status Register224
  - (Usbdevintst - 0X5000 C200)224
- USB Device Interrupt Enable Register (Usbdevinten - 0X5000 C204)225
- USB Device Interrupt Clear Register (Usbdevintclr - 0X5000 C208)225
- USB Device Interrupt Set Register226
  - 0X5000 C20C)226
- USB Device Interrupt Priority Register (Usbdevintpri - 0X5000 C22C)227
- Endpoint Interrupt Registers227
- USB Endpoint Interrupt Status Register (Usbepintst - 0X5000 C230)227
- USB Endpoint Interrupt Enable Register (Usbepinten - 0X5000 C234)228
- USB Endpoint Interrupt Clear Register (Usbepintclr - 0X5000 C238)229
- USB Endpoint Interrupt Set Register230
  - 0X5000 C23C)230
- USB Endpoint Interrupt Priority Register (Usbepintpri - 0X5000 C240)230
- Endpoint Realization Registers231
- EP RAM Requirements231
- USB Realize Endpoint Register232
  - 0X5000 C244)232
  - C248)233
  - 0X5000 C24C)233
- USB Transfer Registers234
- USB Receive Data Register (Usbrxdata - 0X5000 C218)234
- USB Receive Packet Length Register (Usbrxplen - 0X5000 C220)234
- USB Transmit Data Register (Usbtxdata - 0X5000 C21C)234
- USB Transmit Packet Length Register (Usbtxplen - 0X5000 C224)235
- USB Control Register235
  - C228)235
- SIE Command Code Registers236
- USB Command Code Register236
  - 0X5000 C210)236
- USB Command Data Register236
  - 0X5000 C214)236
- DMA Registers236
- USB DMA Request Status Register236
  - 0X5000 C250)236
- USB DMA Request Clear Register237
  - 0X5000 C254)237
- USB DMA Request Set Register238
  - 0X5000 C258)238
- USB UDCA Head Register238
  - C280)238
- USB EP DMA Status Register238
  - 0X5000 C284)238
- USB EP DMA Enable Register239
  - 0X5000 C288)239
- USB EP DMA Disable Register239
  - 0X5000 C28C)239
- USB DMA Interrupt Status Register239
  - 0X5000 C290)239
- USB DMA Interrupt Enable Register (Usbdmainten - 0X5000 C294)240
- USB End of Transfer Interrupt Status Register (Usbeotintst - 0X5000 C2A0)240
- USB End of Transfer Interrupt Clear Register (Usbeotintclr - 0X5000 C2A4)241
- USB End of Transfer Interrupt Set Register (Usbeotintset - 0X5000 C2A8)241
- USB New DD Request Interrupt Status Register (Usbnddrintst - 0X5000 C2AC)241
- USB New DD Request Interrupt Clear Register (Usbnddrintclr - 0X5000 C2B0)241
- USB New DD Request Interrupt Set Register (Usbnddrintset - 0X5000 C2B4)241
- USB System Error Interrupt Status Register (Usbsyserrintst - 0X5000 C2B8)242
- USB System Error Interrupt Clear Register (Usbsyserrintclr - 0X5000 C2BC)242
- USB System Error Interrupt Set Register (Usbsyserrintset - 0X5000 C2C0)242
Interrupt Handling242
- Slave Mode243
- DMA Mode243
Serial Interface Engine Command Description245
- Set Address246
  - Byte)246
- Configure Device246
- Set Mode (Command: 0Xf3, Data: Write 1 Byte)247
- Read Current Frame Number (Command: 0Xf5, Data: Read 1 or 2 Bytes)247
- Read Test Register (Command: 0Xfd, Data: Read 2 Bytes)248
- Set Device Status (Command: 0Xfe, Data: Write 1 Byte)248
- Get Device Status (Command: 0Xfe, Data: Read 1 Byte)249
- Get Error Code (Command: 0Xff, Data: Read 1 Byte)249
- Read Error Status (Command: 0Xfb, Data: Read 1 Byte)250
- Select Endpoint (Command: 0X00 - 0X1F, Data: Read 1 Byte (Optional))250
- Select Endpoint/Clear Interrupt (Command: 0X40 - 0X5F, Data: Read 1 Byte)251
- Set Endpoint Status (Command: 0X40 - 0X55, Data: Write 1 Byte (Optional))252
- Clear Buffer252
  - (Optional))252
- Validate Buffer253
  - None)253
USB Device Controller Initialization253
Slave Mode Operation254
- Interrupt Generation254
- Data Transfer for out Endpoints255
- Data Transfer for in Endpoints255
DMA Operation255
- Transfer Terminology256
- USB Device Communication Area256
- Triggering the DMA Engine257
- The DMA Descriptor257
- Next_Dd_Pointer258
- Dma_Mode258
- Next_Dd_Valid258
- Isochronous_Endpoint259
- Max_Packet_Size259
- Dma_Buffer_Length259
- Dma_Buffer_Start_Addr259
- Dd_Retired259
- Dd_Status259
- Packet_Valid260
- Ls_Byte_Extracted260
- Ms_Byte_Extracted260
- Present_Dma_Count260
- Message_Length_Position260
- Isochronous_Packetsize_Memory_Address260
- Non-Isochronous Endpoint Operation260
- Setting up DMA Transfers260
- Finding DMA Descriptor261
- Transferring the Data261
- Optimizing Descriptor Fetch261
- Ending the Packet Transfer261
- No_Packet DD262
- Isochronous Endpoint Operation262
- Setting up DMA Transfers262
- Finding the DMA Descriptor262
- Transferring the Data263
  - OUT Endpoints263
  - IN Endpoints263
- DMA Descriptor Completion263
- Isochronous out Endpoint Operation263
  - Example263
- Auto Length Transfer Extraction (ATLE) Mode Operation264
  - OUT Transfers in ATLE Mode265
  - IN Transfers in ATLE Mode266
- Setting up the DMA Transfer266
- Finding the DMA Descriptor266
- Transferring the Data266
  - OUT Endpoints266
  - IN Endpoints266
- Ending the Packet Transfer267
  - OUT Endpoints267
  - IN Endpoints267
Double Buffered Endpoint Operation267
- Bulk Endpoints267
- Isochronous Endpoints269
Chapter 12 : Lpc176X/5X USB Host Controller270
How to Read this Chapter270
Basic Configuration270
Introduction270
- Features271
- Architecture271
Interfaces271
- Pin Description272
- USB Host Usage Note272
- Software Interface272
- Register Map272
- USB Host Register Definitions273
Chapter 13: Lpc176X/5X USB OTG274
How to Read this Chapter274
Basic Configuration274
Introduction274
Features274
Architecture275
Modes of Operation275
Pin Configuration276
- Connecting the USB Port to an External OTG Transceiver276
- Connecting USB as a Host277
- Connecting USB as Device277
Register Description278
USB Interrupt Status Register278
- 0X5000 C1C0)278
- OTG Interrupt Status Register (Otgintst - 0X5000 C100)279
- OTG Interrupt Enable Register (Otginten - 0X5000 C104)279
- OTG Interrupt Set Register (Otgintset - 0X5000 C20C)280
- OTG Interrupt Clear Register (Otgintclr - 0X5000 C10C)280
- OTG Status and Control Register (Otgstctrl - 0X5000 C110)280
- OTG Timer Register (Otgtmr - 0X5000 C114)281
- OTG Clock Control Register (Otgclkctrl - 0X5000 CFF4)281
- OTG Clock Status Register (Otgclkst - 0X5000 CFF8)282
  - C300)282
  - C300)283
- I2C Status Register (I2C_STS - 0X5000 C304)283
  - C308)285
- I2C Clock High Register (I2C_CLKHI - 0X5000 C30C)286
- I2C Clock Low Register (I2C_CLKLO - 0X5000 C310)286
- Interrupt Handling286
HNP Support287
- B-Device: Peripheral to Host Switching288
  - Remove D+ Pull-Up290
  - Add D+ Pull-Up291
- A-Device: Host to Peripheral HNP Switching291
Clocking and Power Management295
- Device Clock Request Signals296
- Host Clock Request Signals297
- Power-Down Mode Support297
USB OTG Controller Initialization297
Chapter 14 : Lpc176X/5X UART0/2/3299
Basic Configuration299
Features299
Pin Description300
Register Description300
- Uartn Receiver Buffer Register (U0RBR - 0X4000 C000, U2RBR - 0X4009 8000, U3RBR - 0X4009 C000 When DLAB = 0)302
- Uartn Transmit Holding Register (U0THR - 0X4000 C000, U2THR - 0X4009 8000, U3THR - 0X4009 C000 When DLAB = 0)302
- Uartn Divisor Latch LSB Register302
  - When DLAB = 1)302
- Uartn Interrupt Enable Register (U0IER - 0X4000 C004, U2IER - 0X4009 8004, U3IER - 0X4009 C004 When DLAB = 0)303
- Uartn Interrupt Identification Register (U0IIR - 0X4000 C008, U2IIR - 0X4009 8008, U3IIR - 0X4009 C008)304
- Uartn FIFO Control Register (U0FCR - 0X4000 C008, U2FCR - 0X4009 8008, U3FCR - 0X4009 C008)306
- DMA Operation306
  - UART Receiver DMA306
  - UART Transmitter DMA307
- Uartn Line Control Register (U0LCR - 0X4000 C00C, U2LCR - 0X4009 800C, U3LCR - 0X4009 C00C)307
- Uartn Line Status Register (U0LSR - 0X4000 C014, U2LSR - 0X4009 8014, U3LSR - 0X4009 C014)307
- Uartn Scratch Pad Register (U0SCR - 0X4000 C01C, U2SCR - 0X4009 801C U3SCR - 0X4009 C01C)309
- Uartn Auto-Baud Control Register (U0ACR - 14.5 0X4000 C020, U2ACR - 0X4009 8020, U3ACR - 0X4009 C020)309
- Auto-Baud310
- Auto-Baud Modes311
- Uartn Irda Control Register (U0ICR - 0X4000 C024, U2ICR - 0X4009 8024, U3ICR - 0X4009 C024)312
- Uartn Fractional Divider Register (U0FDR - 0X4000 C028, U2FDR - 0X4009 8028, U3FDR - 0X4009 C028)313
- Baud Rate Calculation314
- Example 2: PCLK = 12 Mhz, BR = 115200316
- Uartn Transmit Enable Register (U0TER - 0X4000 C030, U2TER - 0X4009 8030, U3TER - 0X4009 C030)316
Architecture317
Chapter 15: Lpc176X/5X UART1319
Basic Configuration319
Features319
Pin Description320
Register Description321
- UART1 Receiver Buffer Register (U1RBR - 0X4001 0000, When DLAB = 0)322
- UART1 Transmitter Holding Register (U1THR - 0X4001 0000 When DLAB = 0)322
- UART1 Divisor Latch LSB and MSB Registers (U1DLL - 0X4001 0000 and U1DLM - 0X4001 0004, When DLAB = 1)322
- UART1 Interrupt Enable Register (U1IER - 0X4001 0004, When DLAB = 0)323
- UART1 Interrupt Identification Register (U1IIR - 0X4001 0008)324
- UART1 FIFO Control Register (U1FCR - 0X4001 0008)326
- DMA Operation326
  - UART Receiver DMA327
  - UART Transmitter DMA327
- UART1 Line Control Register (U1LCR - 0X4001 000C)327
- UART1 Modem Control Register (U1MCR - 0X4001 0010)327
- Auto-Flow Control328
- Auto-RTS328
- Auto-CTS329
- UART1 Line Status Register (U1LSR - 0X4001 0014)330
- UART1 Modem Status Register (U1MSR - 0X4001 0018)331
- UART1 Scratch Pad Register (U1SCR - 0X4001 001C)332
- UART1 Auto-Baud Control Register (U1ACR - 0X4001 0020)332
- Auto-Baud333
- Auto-Baud Modes334
- UART1 Fractional Divider Register (U1FDR - 0X4001 0028)335
- Baud Rate Calculation336
- Example 2: PCLK = 12 Mhz, BR = 115200338
- UART1 Transmit Enable Register (U1TER - 0X4001 0030)338
- UART1 RS485 Control Register (U1RS485CTRL - 0X4001 004C)339
- UART1 RS-485 Address Match Register (U1RS485ADRMATCH - 0X4001 0050)340
- UART1 RS-485 Delay Value Register (U1RS485DLY - 0X4001 0054)340
- RS-485/EIA-485 Modes of Operation340
  - RS-485/EIA-485 Normal Multidrop Mode340
  - (Nmm)340
  - Mode340
  - RS-485/EIA-485 Auto Direction Control341
  - RS485/EIA-485 Driver Delay Time341
  - RS485/EIA-485 Output Inversion342
Architecture342
Chapter 16: Lpc176X/5X CAN1/2344
Basic Configuration344
CAN Controllers344
Features344
- General CAN Features344
- CAN Controller Features345
- Acceptance Filter Features345
Pin Description345
CAN Controller Architecture345
- APB Interface Block (AIB)346
- Interface Management Logic (IML)346
- Transmit Buffers (TXB)346
- Receive Buffer (RXB)347
- Error Management Logic (EML)348
- Bit Timing Logic (BTL)348
- Bit Stream Processor (BSP)348
- CAN Controller Self-Tests348
  - Global Self Test349
  - Local Self Test349
Memory Map of the CAN Block350
CAN Controller Registers350
- CAN Mode Register (CAN1MOD - 0X4004 4000, CAN2MOD - 0X4004 8000)352
- CAN Command Register (CAN1CMR - 0X4004 X004, CAN2CMR - 0X4004 8004)354
- CAN Global Status Register (CAN1GSR - 0X4004 X008, CAN2GSR - 0X4004 8008)355
  - RX Error Counter357
  - TX Error Counter357
- CAN Interrupt and Capture Register (CAN1ICR - 0X4004 400C, CAN2ICR - 0X4004 800C)358
- CAN Interrupt Enable Register (CAN1IER - 0X4004 4010, CAN2IER - 0X4004 8010)361
- CAN Bus Timing Register (CAN1BTR -362
- CAN Error Warning Limit Register (CAN1EWL - 0X4004 4018, CAN2EWL - 0X4004 8018)363
- CAN Status Register (CAN1SR - 0X4004 401C, CAN2SR - 0X4004 801C)364
- CAN Receive Frame Status Register (CAN1RFS - 0X4004 4020, CAN2RFS - 0X4004 8020)365
- ID Index Field366
- CAN Receive Identifier Register (CAN1RID -366
- CAN Receive Data Register a (CAN1RDA -367
- CAN Receive Data Register B (CAN1RDB -367
- CAN Transmit Frame Information Register367
  - Automatic Transmit Priority Detection368
  - Tx DLC368
- CAN Transmit Identifier Register369
  - 0X4004 80[34/44/54])369
- CAN Transmit Data Register a (CAN1TDA[1/2/3] - 0X4004 40[38/48/58], CAN2TDA[1/2/3] - 0X4004 80[38/48/58])369
- CAN Transmit Data Register B370
  - 0X4004 80[3C/4C/5C])370
- CAN Sleep Clear Register (CANSLEEPCLR - 0X400F C110)370
- CAN Wake-Up Flags Register (CANWAKEFLAGS - 0X400F C114)371
CAN Controller Operation371
- Error Handling371
- Sleep Mode371
- Interrupts372
- Transmit Priority372
Centralized CAN Registers372
- Central Transmit Status Register (Cantxsr - 0X4004 0000)373
- Central Receive Status Register (Canrxsr - 0X4004 0004)373
- Central Miscellaneous Status Register (CANMSR - 0X4004 0008)374
Global Acceptance Filter374
Acceptance Filter Modes374
- Acceptance Filter off Mode375
- Acceptance Filter Bypass Mode375
- Acceptance Filter Operating Mode375
- Fullcan Mode375
Sections of the ID Look-Up Table RAM375
ID Look-Up Table RAM376
Acceptance Filter Registers378
- Acceptance Filter Mode Register (AFMR - 0X4003 C000)378
- Section Configuration Registers378
- Standard Frame Individual Start Address Register (Sff_Sa - 0X4003 C004)379
- Standard Frame Group Start Address Register (Sff_Grp_Sa - 0X4003 C008)379
- Extended Frame Start Address Register379
  - 0X4003 C00C)379
- Extended Frame Group Start Address Register (Eff_Grp_Sa - 0X4003 C010)380
- End of AF Tables Register (Endoftable - 0X4003 C014)380
- Status Registers380
- LUT Error Address Register (Luterrad - 0X4003 C018)381
- LUT Error Register (Luterr - 0X4003 C01C)381
- Global Fullcaninterrupt Enable Register381
  - 0X4003 C020)381
- Fullcan Interrupt and Capture Registers (FCANIC0 - 0X4003 C024 and FCANIC1 - 0X4003 C028)381
Configuration and Search Algorithm382
- Acceptance Filter Search Algorithm382
Fullcan Mode383
- Fullcan Message Layout385
- Fullcan Interrupts387
- Fullcan Message Interrupt Enable Bit387
- Message Lost Bit and CAN Channel Number388
- Setting the Interrupt Pending Bits389
- Clearing the Interrupt Pending Bits389
- Setting the Message Lost Bit of a Fullcan Message Object (Msglost 63 to 0)389
- Clearing the Message Lost Bit of a Fullcan Message Object (Msglost 63 to 0)389
- Set and Clear Mechanism of the Fullcan Interrupt389
- Scenario 1: Normal Case, no Message Lost . 389 16.16.3.2 Scenario 2: Message Lost390
  - By Semaphore Bits391
- Scenario 3.1: Message Gets Overwritten Indicated by Semaphore Bits and Message Lost391
  - By Message Lost392
- Scenario 4: Clearing Message Lost Bit393
Examples of Acceptance Filter Tables and ID Index Values394
- Example 1: Only One Section Is Used394
- Example 2: All Sections Are Used394
- Example 3: more than One but Not All Sections Are Used394
- Configuration Example 4395
- Configuration Example 5395
- Configuration Example 6396
- Configuration Example 7398
- Look-Up Table Programming Guidelines400
Chapter 17: Lpc176X/5X SPI402
Basic Configuration402
Features402
SPI Overview402
Pin Description403
SPI Data Transfers403
SPI Peripheral Details405
- General Information405
- Master Operation405
- Slave Operation406
- Exception Conditions406
Register Description407
- SPI Control Register407
- SPI Status Register409
- SPI Data Register (S0SPDR - 0X4002 0008)409
- SPI Clock Counter Register (S0SPCCR - 0X4002 000C)409
- SPI Test Control Register410
- SPI Test Status Register (SPTSR - 0X4002 0014)410
SPI Interrupt Register411
- 411411
Architecture412
Chapter 18: Lpc176X/5X SSP0/1413
Basic Configuration413
Features413
Description413
Pin Descriptions414
Bus Description414
- Texas Instruments Synchronous Serial Frame414
  - Format414
- SPI Frame Format415
  - Control415
- SPI Format with CPOL=0,CPHA=0416
- SPI Format with CPOL=0,CPHA=1417
- SPI Format with CPOL = 1,CPHA = 0417
- SPI Format with CPOL = 1,CPHA = 1419
  - Format419
- Setup and Hold Time Requirements on CS with Respect to SK in Microwire Mode421
Register Description422
- Sspn Control Register 0 (SSP0CR0 -422
- Sspn Control Register 1 (SSP0CR1 -423
- Sspn Data Register (SSP0DR - 0X4008 8008424
- Sspn Status Register (SSP0SR - 0X4008 800C, SSP1SR - 0X4003 000C)425
- Sspn Interrupt Mask Set/Clear Register (SSP0IMSC - 0X4008 8014, SSP1IMSC - 0X4003 0014)425
- Sspn Raw Interrupt Status Register (SSP0RIS -426
- Sspn Masked Interrupt Status Register (SSP0MIS - 0X4008 801C, SSP1MIS - 0X4003 001C)426
- Sspn Interrupt Clear Register (SSP0ICR -427
Chapter 19 : Lpc176X/5X I2C0/1/2429
Basic Configuration429
Features429
Applications430
Description430
- I 2 C FAST Mode Plus431
Pin Description431
I 2 C Operating Modes432
- Master Transmitter Mode432
- Master Receiver Mode433
- Slave Receiver Mode434
- Slave Transmitter Mode435
I 2 C Implementation and Operation435
- Input Filters and Output Stages435
- Address Registers, I2ADR0 to I2ADR3436
- Address Mask Registers, I2MASK0 to I2MASK3437
- Comparator437
- Shift Register, I2DAT437
- Arbitration and Synchronization Logic437
- Serial Clock Generator438
- Timing and Control439
- Control Register, I2CONSET and I2CONCLR 439 Status Decoder and Status Register439
Register Description440
- I C000;2, C000; C000;Ontrol Set Register (IC000;2,C000;ONSET: I C000;2, C000;0, IC000;2,C000;0C000;ONSET - 0X4001 C000;000; I C000;2, C000;1, IC000;2,C000;1C000;ONSET - 0X4005 C000;000; I C000;2, C000;C000;2,, IC000;2,C000;C000;2,C000;ONSET - 0X400A 0000)441
- Interrupt in Monitor Mode446
- Loss of Arbitration in Monitor Mode446
- C SCL Low Duty Cycle Register (I2SCLL: I I2C0SCLL: 0X4001 C014; I C1 - I2C1SCLL: 0X4005 C014; I C2 - I2C2SCLL: 0X400A 0014)448
  - Cycle449
Details of I C Operating Modes450
- Master Transmitter Mode451
- Master Receiver Mode453
- Slave Receiver Mode455
- Slave Transmitter Mode457
- Detailed State Tables458
- Miscellaneous States463
- I2STAT = 0Xf8463
- I2STAT = 0X00463
- Some Special Cases463
- Simultaneous Repeated START Conditions from Two Masters463
- Data Transfer after Loss of Arbitration464
- Forced Access to the I C-Bus464
- C-Bus Obstructed by a LOW Level on SCL or SDA464
- Bus Error464
- I 2 C State Service Routines466
- Initialization466
- I 2 C Interrupt Service466
- The State Service Routines466
- Adapting State Services to an Application466
Software Example467
- Initialization Routine467
- Start Master Transmit Function467
- Start Master Receive Function467
- C Interrupt Routine467
- Non Mode Specific States467
- State: 0X00467
- Master States468
- State: 0X08468
- State: 0X10468
- Master Transmitter States468
- State: 0X18468
- State: 0X20469
- State: 0X28469
- State: 0X30469
- State: 0X38469
- Master Receive States469
- State: 0X40469
- State: 0X48470
- State: 0X50470
- State: 0X58470
- Slave Receiver States470
- State: 0X60470
- State: 0X68471
- State: 0X70471
- State: 0X78471
- State: 0X80471
- State: 0X88472
- State: 0X90472
- State: 0X98472
- State: 0Xa0472
- Slave Transmitter States472
- State: 0Xa8472
- State: 0Xb0473
- State: 0Xb8473
- State: 0Xc0473
- State: 0Xc8473
Chapter 20 : Lpc176X/5X I2S474
Basic Configuration474
Features474
Description475
Pin Descriptions476
Register Description477
- Digital Audio Output Register (I2SDAO - 0X400A 8000)477
- Digital Audio Input Register477
  - 0X400A 8004)478
- Transmit FIFO Register (I2STXFIFO - 0X400A 8008)478
- Receive FIFO Register (I2SRXFIFO - 0X400A 800C)478
- Status Feedback Register (I2SSTATE - 0X400A 8010)479
- DMA Configuration Register 1 (I2SDMA1 - 0X400A 8014)479
- DMA Configuration Register 2 (I2SDMA2 - 0X400A 8018)480
- Interrupt Request Control Register (I2SIRQ - 0X400A 801C)480
- Transmit Clock Rate Register (I2STXRATE - 0X400A 8020)480
- Notes on Fractional Rate Generators481
  - Receive Clock Rate Register (I2SRXRATE - 0X400A 8024)481
- Transmit Clock Bit Rate Register (I2STXBITRATE - 0X400A 8028)482
- Receive Clock Bit Rate Register (I2SRXBITRATE - 0X400A 802C)482
- Transmit Mode Control Register (I2STXMODE - 0X400A 8030)482
- Receive Mode Control Register (I2SRXMODE - 0X400A 8034)483
S Transmit and Receive Interfaces484
S Operating Modes485
FIFO Controller489
Chapter 21: Lpc176X/5X Timer 0/1/2/3491
Basic Configuration491
Features491
Applications492
Description492
Pin Description492
- Multiple CAP and MAT Pins492
Register Description493
- Interrupt Register (T[0/1/2/3]IR - 0X4000 4000, 0X4000 8000, 0X4009 0000, 0X4009 4000)494
- Timer Control Register494
  - 0X4000 4004, 0X4000 8004, 0X4009 0004, 0X4009 4004)494
- Count Control Register (T[0/1/2/3]CTCR - 0X4000 4070, 0X4000 8070, 0X4009 0070, 0X4009 4070)495
- Timer Counter496
- Prescale Counter Register (T0PC - T3PC, 0X4000 4010, 0X4000 8010, 0X4009 0010, 0X4009 4010)496
- Match Registers (MR0 - MR3)497
- Match Control Register (T[0/1/2/3]MCR - 0X4000 4014, 0X4000 8014, 0X4009 0014, 0X4009 4014)497
- Capture Registers (CR0 - CR1)498
  - Capture Control Register (T[0/1/2/3]CCR - 0X4000 4028, 0X4000 8028, 0X4009 0028, 0X4009 4028)498
- External Match Register (T[0/1/2/3]EMR - 0X4000 403C, 0X4000 803C, 0X4009 003C, 0X4009 403C)498
- DMA Operation499
Example Timer Operation500
Architecture501
Chapter 22 : Lpc176X/5X Repetitive Interrupt Timer (RIT)502
Features502
Description502
Register Description502
- RI Compare Value Register (RICOMPVAL - 0X400B 0000)502
- RI Mask Register (RIMASK - 0X400B 0004)502
- RI Control Register (RICTRL - 0X400B 0008)503
  - 503503
RI Timer Operation503
Description505
Chapter 23 : Lpc176X/5X System Tick Timer505
Operation505
Basic Configuration505
Features505
Register Description506
- System Timer Control and Status Register (STCTRL - 0Xe000 E010)506
- System Timer Reload Value Register (STRELOAD - 0Xe000 E014)507
- System Timer Current Value Register (STCURR - 0Xe000 E018)507
- System Timer Calibration Value Register (STCALIB - 0Xe000 E01C)507
Example Timer Calculations509
- Example 1)509
- Example 2)509
- Example 3)509
- Example 4)509
Chapter 24: Lpc176X/5X Pulse Width Modulator (PWM)510
Basic Configuration510
Features510
Description511
Sample Waveform with Rules for Single and Double Edge Control513
- Rules for Single Edge Controlled PWM Outputs514
- Rules for Double Edge Controlled PWM Outputs514
Pin Description514
Register Description515
- PWM Interrupt Register (PWM1IR - 0X4001 8000)516
- PWM Timer Control Register (PWM1TCR 0X4001 8004)517
- PWM Count Control Register (PWM1CTCR - 0X4001 8070)517
- PWM Match Control Register (PWM1MCR - 0X4001 8014)518
- PWM Capture Control Register (PWM1CCR - 0X4001 8028)519
- PWM Control Register (PWM1PCR - 0X4001 804C)520
- PWM Latch Enable Register (PWM1LER - 0X4001 8050)521
Chapter 25: Lpc176X/5X Motor Control PWM523
Introduction523
Description523
Pin Description523
Block Diagram524
Configuring Other Modules for MCPWM Use525
General Operation525
Register Description526
- MCPWM Control Register527
- MCPWM Control Read Address (MCCON - 0X400B 8000)527
- MCPWM Control Set Address528
  - 0X400B 8004)528
  - 0X400B 8008)529
- MCPWM Capture Control Register529
- MCPWM Capture Control Read Address (MCCAPCON - 0X400B 800C)529
- MCPWM Capture Control Set Address (MCCAPCON_SET - 0X400B 8010)530
- MCPWM Capture Control Clear Address (MCCAPCON_CLR - 0X400B 8014)530
- MCPWM Interrupt Registers530
- MCPWM Interrupt Enable Read Address530
- MCPWM Interrupt Enable Set Address531
- MCPWM Interrupt Enable Clear Address (MCINTEN_CLR - 0X400B 8058)531
- MCPWM Interrupt Flags Read Address (MCINTF - 0X400B 8068)531
- MCPWM Interrupt Flags Set Address (MCINTF_SET - 0X400B 806C)531
- MCPWM Interrupt Flags Clear Address (MCINTF_CLR - 0X400B 8070)531
- MCPWM Count Control Register532
- MCPWM Count Control Read Address (MCCNTCON - 0X400B 805C)532
- MCPWM Count Control Set Address (MCCNTCON_SET - 0X400B 8060)533
- MCPWM Count Control Clear Address (MCCNTCON_CLR - 0X400B 8064)533
- MCPWM Timer/Counter 0-2 Registers533
- MCPWM Limit 0-2 Registers534
- Match and Limit Write and Operating Registers534
- MCPWM Match 0-2 Registers535
- Match Register in Edge-Aligned Mode535
- Match Register in Center-Aligned Mode535
- And 100% Duty Cycle535
- MCPWM Dead-Time Register (MCDT - 0X400B 803C)536
- MCPWM Commutation Pattern Register (MCCP - 0X400B 8040)536
- MCPWM Capture Registers537
- MCPWM Capture Read Addresses537
  - 0X400B 8074)537
PWM Operation538
- Pulse-Width Modulation538
- Shadow Registers and Simultaneous Updates 540 Fast Abort (ABORT)540
- Capture Events540
- External Event Counting (Counter Mode)541
- Three-Phase DC Mode541
- Three Phase AC Mode542
- Interrupts543
Chapter 26: Lpc176X/5X Quadrature Encoder Interface (QEI)544
Basic Configuration544
Features544
Introduction544
Functional Description546
- Input Signals546
- Quadrature Input Signals546
- Digital Input Filtering547
- Position Capture547
- Velocity Capture547
- Velocity Compare548
Pin Description549
Register Description550
- Register Summary550
- Control Registers551
- C000)551
- C008)551
- QEI Status Register (QEISTAT - 0X400B C004)551
- Position, Index and Timer Registers552
  - C00C)552
- QEI Maximum Position Register (QEIMAXPOS - 0X400B C010)552
- QEI Position Compare Register 0 (CMPOS0 - 0X400B C014)552
- QEI Position Compare Register 1 (CMPOS1 - 0X400B C018)552
- QEI Position Compare Register 2 (CMPOS2 - 0X400B C01C)553
- QEI Index Count Register (INXCNT - 0X400B C020)553
  - C024)553
- QEI Timer Reload Register (QEILOAD - 0X400B C028)553
- QEI Timer Register (QEITIME - 0X400B C02C)553
  - C030)554
  - C034)554
  - 0X400B C038)554
  - C03C)554
- Interrupt Registers555
- QEI Interrupt Status Register (QEIINTSTAT)555
- QEI Interrupt Set Register (QEISET - 0X400B CFEC)555
- QEI Interrupt Clear Register (QEICLR - 0X400B CFE8)556
- QEI Interrupt Enable Register (QEIIE - 0X400B CFE4)556
- QEI Interrupt Enable Set Register (QEIIES - 0X400B CFDC)557
- QEI Interrupt Enable Clear Register (QEIIEC - 0X400B CFD8)558
Basic Configuration559
Chapter 27 : Lpc176X/5X Real-Time Clock (RTC) and Backup Registers559
Features559
Description559
Architecture560
Pin Description561
Register Description561
- RTC Interrupts563
- Miscellaneous Register Group563
- Interrupt Location Register (ILR - 0X4002 4000)563
- Clock Control Register (CCR - 0X4002 4008)563
- Counter Increment Interrupt Register (CIIR - 0X4002 400C)564
- Alarm Mask Register (AMR - 0X4002 4010)564
  - 0X4002 405C)565
  - 0X4002 4058)565
- Consolidated Time Registers566
- Consolidated Time Register 0 (CTIME0 - 0X4002 4014)566
- Consolidated Time Register 1 (CTIME1 - 0X4002 4018)566
- Consolidated Time Register 2 (CTIME2 - 0X4002 401C)566
- Time Counter Group567
- Leap Year Calculation567
- Calibration Register (CALIBRATION - Address 0X4002 4040)567
- Calibration Procedure568
  - Backward Calibration568
  - Forward Calibration568
- General Purpose Registers569
- General Purpose Registers 0 to 4 (GPREG0 to GPREG4 - Addresses 0X4002 4044 to 0X4002 4054)569
- Alarm Register Group569
RTC Usage Notes569
Chapter 28: Lpc176X/5X Watchdog Timer (WDT)570
Features570
Applications570
Description571
Register Description571
- Watchdog Mode Register (WDMOD - 0X4000 0000)572
- Watchdog Timer Constant Register (WDTC - 0X4000 0004)573
- Watchdog Feed Register (WDFEED - 0X4000 0008)573
- Watchdog Timer Value Register (WDTV - 0X4000 000C)573
- Watchdog Timer Clock Source Selection Register573
Block Diagram574
Chapter 29 : Lpc176X/5X Analog-To-Digital Converter (ADC)575
Basic Configuration575
Features575
Description575
Pin Description576
Register Description577
- A/D Control Register (AD0CR - 0X4003 4000)578
- A/D Global Data Register (AD0GDR - 0X4003 4004)579
- A/D Interrupt Enable Register (AD0INTEN - 0X4003 400C)579
- A/D Data Registers (AD0DR0 to AD0DR7 - 0X4003 4010 to 0X4003 402C)580
- A/D Status Register (ADSTAT - 0X4003 4030)581
- A/D Trim Register (ADTRIM - 0X4003 4034)581
Operation582
- Hardware-Triggered Conversion582
- Interrupts582
- Accuracy Vs. Digital Receiver582
- DMA Control582
Chapter 30 : Lpc176X/5X Digital-To-Analog Converter (DAC)583
Pin Description583
Basic Configuration583
Features583
Register Description584
- C000)584
- D/A Converter Control Register (DACCTRL - 0X4008 C004)584
- D/A Converter Counter Value Register585
Operation585
- DMA Counter585
- Double Buffering585
Chapter 31 : Lpc176X/5X General Purpose DMA (GPDMA)587
Basic Configuration587
Introduction587
Features587
Functional Description588
- DMA Controller Functional Description588
- AHB Slave Interface588
- Control Logic and Register Bank589
- DMA Request and Response Interface589
- Channel Logic and Channel Register Bank589
- Interrupt Request589
- AHB Master Interface589
- Bus and Transfer Widths589
- Endian Behavior589
- Error Conditions591
- Channel Hardware592
- DMA Request Priority592
- Interrupt Generation592
- DMA System Connections592
- DMA Request Signals592
- DMA Response Signals592
- DMA Request Connections593
Register Description594
- DMA Interrupt Status Register (Dmacintstat - 0X5000 4000)596
- DMA Interrupt Terminal Count Request Status Register (Dmacinttcstat - 0X5000 4004)596
- DMA Interrupt Terminal Count Request Clear Register (Dmacinttcclear - 0X5000 4008)596
- DMA Interrupt Error Status Register (Dmacinterrstat - 0X5000 400C)596
- DMA Interrupt Error Clear Register (Dmacinterrclr - 0X5000 4010)597
- DMA Raw Interrupt Terminal Count Status Register (Dmacrawinttcstat - 0X5000 4014)597
- DMA Raw Error Interrupt Status Register (Dmacrawinterrstat - 0X5000 4018)597
- DMA Enabled Channel Register (Dmacenbldchns - 0X5000 401C)598
- DMA Software Burst Request Register (Dmacsoftbreq - 0X5000 4020)598
- DMA Software Single Request Register (Dmacsoftsreq - 0X5000 4024)599
- DMA Software Last Burst Request Register (Dmacsoftlbreq - 0X5000 4028)599
- DMA Software Last Single Request Register (Dmacsoftlsreq - 0X5000 402C)599
- DMA Configuration Register (Dmacconfig - 0X5000 4030)600
- DMA Synchronization Register (Dmacsync - 0X5000 4034)600
- DMA Request Select Register (Dmareqsel - 0X400F C1C4)601
- DMA Channel Registers601
- DMA Channel Source Address Registers (Dmaccxsrcaddr - 0X5000 41X0)602
- DMA Channel Destination Address Registers (Dmaccxdestaddr - 0X5000 41X4)602
- DMA Channel Linked List Item Registers (Dmaccxlli - 0X5000 41X8)602
- DMA Channel Control Registers (Dmaccxcontrol - 0X5000 41Xc)603
- Protection and Access Information603
- DMA Channel Configuration Registers (Dmaccxconfig - 0X5000 41X0)605
- Lock Control607
- Transfer Type607
Using the DMA Controller608
- Programming the DMA Controller608
- Enabling the DMA Controller608
- Disabling the DMA Controller608
- Enabling a DMA Channel608
- Disabling a DMA Channel608
  - Disabling a DMA Channel and Losing Data in the FIFO608
  - Disabling the DMA Channel Without Losing Data in the FIFO608
- Setting up a New DMA Transfer608
- Halting a DMA Channel609
- Programming a DMA Channel609
- Flow Control609
- Peripheral-To-Memory or Memory-To-Peripheral DMA Flow610
- Peripheral-To-Peripheral DMA Flow610
- Memory-To-Memory DMA Flow611
- Interrupt Requests611
- Hardware Interrupt Sequence Flow612
- Address Generation612
- Word-Aligned Transfers Across a Boundary . 612 Scatter/Gather612
- Linked List Items613
- Programming the DMA Controller for Scatter/Gather DMA613
- Example of Scatter/Gather DMA613
Chapter 32: Lpc176X/5X Flash Memory Interface and Programming616
Introduction616
Features616
Description616
- Memory Map after any Reset617
- Criterion for Valid User Code617
- Communication Protocol618
- ISP Command Format618
- ISP Response Format618
- ISP Data Format618
- ISP Flow Control619
- ISP Command Abort619
- Interrupts During IAP619
- RAM Used by ISP Command Handler619
- RAM Used by IAP Command Handler619
Boot Process Flowchart620
Sector Numbers621
Code Read Protection (CRP)622
ISP Commands624
- Unlock <Unlock Code624
- Set Baud Rate <Baud Rate> <Stop Bit625
- Echo <Setting625
- Write to RAM <Start Address> <Number of Bytes625
- Read Memory <Address> <No. of Bytes626
- Prepare Sector(S) for Write Operation <Start Sector Number> <End Sector Number627
- Copy RAM to Flash <Flash Address> <RAM Address> <No of Bytes627
- Go <Address> <Mode628
- Erase Sector(S) <Start Sector Number> <End Sector Number628
- Blank Check Sector(S) <Sector Number> <End Sector Number629
- Read Part Identification Number629
- Read Boot Code Version Number630
- Read Device Serial Number630
- Compare <Address1> <Address2> <No of Bytes630
- ISP Return Codes631
IAP Commands632
- Prepare Sector(S) for Write Operation634
- Copy RAM to Flash635
- Erase Sector(S)635
- Blank Check Sector(S)636
- Read Part Identification Number636
- Read Boot Code Version Number636
- Read Device Serial Number637
- Compare <Address1> <Address2> <No of Bytes637
- Re-Invoke ISP637
- IAP Status Codes638
JTAG Flash Programming Interface638
Flash Signature Generation639
- Register Description for Signature Generation639
  - Registers640
- Signature Generation Result Registers640
  - 0X0X4008 4FE0)641
  - 0X0X4008 4FE8)641
- Algorithm and Procedure for Signature Generation642
  - Signature Generation642
  - Content Verification642
Chapter 33 : Lpc176X/5X JTAG, Serial Wire Debug (SWD), and Trace643
Features643
Introduction643
Description643
Pin Description643
Debug Notes644
JTAG TAP Identification645
Debug Memory Re-Mapping645
- Memory Mapping Control Register (MEMMAP - 0X400F C040)645
Chapter 34 : Appendix: Cortex-M3 User Guide646
ARM Cortex-M3 User Guide: Introduction646
- About the Processor and Core Peripherals646
- System Level Interface647
- Integrated Configurable Debug647
- Cortex-M3 Processor Features and Benefits Summary648
- Cortex-M3 Core Peripherals648
ARM Cortex-M3 User Guide: Instruction Set649
- Instruction Set Summary649
  - Note649
- Intrinsic Functions652
- About the Instruction Descriptions652
- Operands653
- Restrictions When Using PC or SP653
- Flexible Second Operand653
- Constant653
- Register with Optional Shift654
- Shift Operations654
- Asr655
  - Note655
- Lsr655
- Lsl656
  - Note656
- Ror656
- Rrx657
- Address Alignment657
- PC-Relative Expressions658
  - Note658
- Conditional Execution658
- The Condition Flags659
- Condition Code Suffixes659
- Instruction Width Selection660
- Example: Instruction Width Selection660
- Memory Access Instructions661
- Adr662
- Syntax662
- Operation662
- Restrictions662
- Condition Flags662
- Examples662
- LDR and STR, Immediate Offset663
- Syntax663
- Operation663
- Restrictions664
- Condition Flags664
- Examples665
- LDR and STR, Register Offset666
- Syntax666
- Operation666
- Restrictions666
- Condition Flags667
- Examples667
- LDR and STR, Unprivileged668
- Syntax668
- Operation668
- Restrictions668
- Condition Flags668
- Examples669
- LDR, PC-Relative670
- Syntax670
- Operation670
- Restrictions670
- Condition Flags671
- Examples671
- LDM and STM672
- Syntax672
- Operation672
- Restrictions673
- Condition Flags673
- Examples673
- Incorrect Examples673
- PUSH and POP674
- Syntax674
- Operation674
- Restrictions674
- Condition Flags674
- Examples674
- LDREX and STREX675
- Syntax675
- Operation675
- Restrictions675
- Condition Flags676
- Examples676
- Clrex677
- Syntax677
- Operation677
- Condition Flags677
- Examples677
- General Data Processing Instructions678
- ADD, ADC, SUB, SBC, and RSB679
- Syntax679
- Operation679
- Restrictions679
  - Note680
- Condition Flags680
- Examples680
- Multiword Arithmetic Examples680
- AND, ORR, EOR, BIC, and ORN682
- Syntax682
- Operation682
- Restrictions682
- Condition Flags682
- Examples682
- ASR, LSL, LSR, ROR, and RRX684
- Syntax684
- Operation684
- Restrictions684
- Condition Flags685
- Examples685
- Clz686
- Syntax686
- Operation686
- Restrictions686
- Condition Flags686
- Examples686
- CMP and CMN687
- Syntax687
- Operation687
- Restrictions687
- Condition Flags687
- Examples687
- MOV and MVN688
- Syntax688
- Operation688
- Restrictions689
- Condition Flags689
- Example689
- Movt690
- Syntax690
- Operation690
- Restrictions690
- Condition Flags690
- Examples690
- REV, REV16, REVSH, and RBIT691
- Syntax691
- Operation691
- Restrictions691
- Condition Flags691
- Examples691
- TST and TEQ692
- Syntax692
- Operation692
- Restrictions692
- Condition Flags692
- Examples692
- Multiply and Divide Instructions693
- MUL, MLA, and MLS694
- Syntax694
- Operation694
- Restrictions694
- Condition Flags694
- Examples695
- UMULL, UMLAL, SMULL, and SMLAL696
- Syntax696
- Operation696
- Restrictions696
- Condition Flags696
- Examples697
- SDIV and UDIV698
- Syntax698
- Operation698
- Restrictions698
- Condition Flags698
- Examples698
- Saturating Instructions699
- SSAT and USAT699
- Syntax699
- Operation699
- Restrictions700
- Condition Flags700
- Examples700
- Bitfield Instructions701
- BFC and BFI702
- Syntax702
- Operation702
- Restrictions702
- Condition Flags702
- Examples702
- SBFX and UBFX703
- Syntax703
- Operation703
- Restrictions703
- Condition Flags703
- Examples703
- SXT and UXT704
- Syntax704
- Operation704
- Restrictions704
- Condition Flags704
- Examples705
- Branch and Control Instructions706
- B, BL, BX, and BLX707
- Syntax707
- Operation707
- Restrictions708
- Condition Flags708
- Examples708
- CBZ and CBNZ709
- Syntax709
- Operation709
- Restrictions709
- Condition Flags709
- Examples709
- Syntax710
- Operation710
- Restrictions710
- Condition Flags711
- Example711
- TBB and TBH713
- Syntax713
- Operation713
- Restrictions713
- Condition Flags713
- Examples713
- Miscellaneous Instructions715
- Bkpt716
- Syntax716
- Operation716
- Condition Flags716
- Examples716
- Cps717
- Syntax717
- Operation717
- Restrictions717
- Condition Flags717
- Examples717
- Dmb718
- Syntax718
- Operation718
- Condition Flags718
- Examples718
- Dsb719
- Syntax719
- Operation719
- Condition Flags719
- Examples719
- Isb720
- Syntax720
- Operation720
- Condition Flags720
- Examples720
- Mrs721
- Syntax721
- Operation721
- Restrictions721
- Condition Flags721
- Examples721
- Msr722
- Syntax722
- Operation722
  - Note722
- Restrictions722
- Condition Flags722
- Examples722
- Nop723
- Syntax723
- Operation723
- Condition Flags723
- Examples723
- Sev724
- Syntax724
- Operation724
- Condition Flags724
- Examples724
- Svc725
- Syntax725
- Operation725
- Condition Flags725
- Examples725
- Wfe726
- Syntax726
- Operation726
- Condition Flags726
- Examples726
- Wfi727
- Syntax727
- Operation727
- Condition Flags727
- Examples727
ARM Cortex-M3 User Guide: Processor728
- Programmers Model728
- Processor Mode and Privilege Levels for Software Execution728
- Stacks728
- Core Registers729
- General-Purpose Registers730
- Stack Pointer730
- Link Register730
- Program Counter730
- Program Status Register730
- Exception Mask Registers734
- CONTROL Register735
- Exceptions and Interrupts735
- Data Types736
- The Cortex Microcontroller Software Interface Standard736
- Memory Model737
- Memory Regions, Types and Attributes737
- Memory System Ordering of Memory Accesses738
- Behavior of Memory Accesses739
- Software Ordering of Memory Accesses739
- Bit-Banding740
- Directly Accessing an Alias Region742
- Directly Accessing a Bit-Band Region742
- Memory Endianness743
- Little-Endian Format743
- Synchronization Primitives743
- Programming Hints for the Synchronization Primitives744
- Exception Model746
- Exception States746
- Exception Types746
- Exception Handlers748
- Vector Table749
- Exception Priorities749
- Interrupt Priority Grouping750
- Exception Entry and Return750
- Exception Entry751
- Exception Return752
- Fault Handling754
- Fault Types754
- Fault Escalation and Hard Faults755
- Fault Status Registers and Fault Address Registers755
- Lockup756
- Power Management757
- Entering Sleep Mode757
- Wait for Interrupt757
- Wait for Event757
- Sleep-On-Exit758
- Wakeup from Sleep Mode758
- Wakeup from WFI or Sleep-On-Exit758
- Wakeup from WFE758
- The Wake-Up Interrupt Controller758
- Power Management Programming Hints759
ARM Cortex-M3 User Guide: Peripherals760
- About the Cortex-M3 Peripherals760
- Nested Vectored Interrupt Controller761
- The CMSIS Mapping of the Cortex-M3 NVIC Registers761
- Interrupt Set-Enable Registers762
- Interrupt Clear-Enable Registers762
- Interrupt Set-Pending Registers763
- Interrupt Clear-Pending Registers763
- Interrupt Active Bit Registers764
- Interrupt Priority Registers764
- Software Trigger Interrupt Register765
- Level-Sensitive and Pulse Interrupts765
- Hardware and Software Control of Interrupts766
- NVIC Design Hints and Tips766
- NVIC Programming Hints767
- System Control Block768
- The CMSIS Mapping of the Cortex-M3 SCB Registers768
- Auxiliary Control Register768
- About IT Folding769
- CPUID Base Register769
- Interrupt Control and State Register769
- Vector Table Offset Register771
- Application Interrupt and Reset Control Register772
- Binary Point773
- System Control Register773
- Configuration and Control Register774
- System Handler Priority Registers775
- System Handler Priority Register 1776
- System Handler Priority Register 2776
- System Handler Priority Register 3776
- System Handler Control and State Register776
  - Caution777
- Configurable Fault Status Register778
- Memory Management Fault Status Register778
- Bus Fault Status Register779
- Usage Fault Status Register780
- Hard Fault Status Register782
  - Register782
- Bus Fault Address Register782
- System Control Block Design Hints and Tips783
- System Timer, Systick784
- Systick Control and Status Register784
- Systick Reload Value Register785
- Calculating the RELOAD Value785
- Systick Current Value Register785
- Systick Calibration Value Register785
- Systick Design Hints and Tips786
- Memory Protection Unit787
- MPU Type Register788
- MPU Control Register789
- MPU Region Number Register790
- MPU Region Base Address Register790
- The ADDR Field791
- MPU Region Attribute and Size Register791
- SIZE Field Values792
- MPU Access Permission Attributes793
- MPU Mismatch794
- Updating an MPU Region794
  - Words794
  - Writes795
- Subregions796
- MPU Design Hints and Tips797
- MPU Configuration for a Microcontroller797
ARM Cortex-M3 User Guide: Glossary798
Abbreviations802
Legal Information803
- Definitions803
- Disclaimers803
- Trademarks803
Tables804
Figures816
Contents818

Series	LPC1700
Core	ARM Cortex-M3
Clock Speed	100 MHz
Flash Memory	512 kB
SRAM	64 kB
GPIO Pins	70
ADC Channels	8
ADC Resolution	12-bit
UART	4
SPI	2
I2C	3
Operating Voltage	2.4 V to 3.6 V
PWM Channels	6
Ethernet	Yes
Operating Temperature	-40°C to +85°C
USB	Yes (Device/Host/OTG)
CAN	Yes
Package	LQFP100

NXP Semiconductors LPC1768 - User Manual

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