UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 332 of 841
NXP Semiconductors
UM10360
Chapter 15: LPC176x/5x UART1
15.4.12 UART1 Scratch Pad Register (U1SCR - 0x4001 001C)
The U1SCR has no effect on the UART1 operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the U1SCR has occurred.
15.4.13 UART1 Auto-baud Control Register (U1ACR - 0x4001 0020)
The UART1 Auto-baud Control Register (U1ACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
1 Delta DSR Set upon state change of input DSR. Cleared on an U1MSR read. 0
0 No change detected on modem input, DSR.
1 State change detected on modem input, DSR.
2 Trailing Edge RI Set upon low to high transition of input RI. Cleared on an U1MSR read. 0
0 No change detected on modem input, RI.
1 Low-to-high transition detected on RI.
3 Delta DCD Set upon state change of input DCD. Cleared on an U1MSR read. 0
0 No change detected on modem input, DCD.
1 State change detected on modem input, DCD.
4 CTS Clear To Send State. Complement of input signal CTS. This bit is
connected to U1MCR[1] in modem loopback mode.
0
5 DSR Data Set Ready State. Complement of input signal DSR. This bit is
connected to U1MCR[0] in modem loopback mode.
0
6 RI Ring Indicator State. Complement of input RI. This bit is connected to
U1MCR[2] in modem loopback mode.
0
7 DCD Data Carrier Detect State. Complement of input DCD. This bit is connected
to U1MCR[3] in modem loopback mode.
0
31:8 - Reserved, the value read from a reserved bit is not defined. NA
Table 302: UART1 Modem Status Register (U1MSR - address 0x4001 0018) bit description
Bit Symbol Value Description Reset Value
Table 303: UART1 Scratch Pad Register (U1SCR - address 0x4001 0014) bit description
Bit Symbol Description Reset Value
7:0 Pad A readable, writable byte. 0x00
Table 304: Auto-baud Control Register (U1ACR - address 0x4001 0020) bit description
Bit Symbol Value Description Reset value
0 Start This bit is automatically cleared after auto-baud completion. 0
0 Auto-baud stop (auto-baud is not running).
1 Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
automatically cleared after auto-baud completion.
1 Mode Auto-baud mode select bit. 0
0 Mode 0.
1 Mode 1.