UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 234 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
11.10.5 USB transfer registers
The registers in this group are used for transferring data between endpoint buffers and
RAM in Slave mode operation. See Section 11.14 “
Slave mode operation”.
11.10.5.1 USB Receive Data register (USBRxData - 0x5000 C218)
For an OUT transaction, the CPU reads the endpoint buffer data from this register. Before
reading this register, the RD_EN bit and LOG_ENDPOINT field of the USBCtrl register
should be set appropriately. On reading this register, data from the selected endpoint
buffer is fetched. The data is in little endian format: the first byte received from the USB
bus will be available in the least significant byte of USBRxData. USBRxData is a read-only
register.
11.10.5.2 USB Receive Packet Length register (USBRxPLen - 0x5000 C220)
This register contains the number of bytes remaining in the endpoint buffer for the current
packet being read via the USBRxData register, and a bit indicating whether the packet is
valid or not. Before reading this register, the RD_EN bit and LOG_ENDPOINT field of the
USBCtrl register should be set appropriately. This register is updated on each read of the
USBRxData register. USBRxPLen is a read-only register.
11.10.5.3 USB Transmit Data register (USBTxData - 0x5000 C21C)
For an IN transaction, the CPU writes the endpoint data into this register. Before writing to
this register, the WR_EN bit and LOG_ENDPOINT field of the USBCtrl register should be
set appropriately, and the packet length should be written to the USBTxPlen register. On
writing this register, the data is written to the selected endpoint buffer. The data is in little
endian format: the first byte sent on the USB bus will be the least significant byte of
USBTxData. USBTxData is a write-only register.
Table 215. USB Receive Data register (USBRxData - address 0x5000 C218) bit description
Bit Symbol Description Reset value
31:0 RX_DATA Data received. 0x0000 0000
Table 216. USB Receive Packet Length register (USBRxPlen - address 0x5000 C220) bit description
Bit Symbol Value Description Reset value
9:0 PKT_LNGTH - The remaining number of bytes to be read from the currently selected
endpoint’s buffer. When this field decrements to 0, the RxENDPKT bit will be
set in USBDevIntSt.
0
10 DV Data valid. This bit is useful for isochronous endpoints. Non-isochronous
endpoints do not raise an interrupt when an erroneous data packet is
received. But invalid data packet can be produced with a bus reset. For
isochronous endpoints, data transfer will happen even if an erroneous
packet is received. In this case DV bit will not be set for the packet.
0
0 Data is invalid.
1 Data is valid.
11 PKT_RDY - The PKT_LNGTH field is valid and the packet is ready for reading. 0
31:12 - - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA
To Next Page
Loading...
