NXP Semiconductors LPC1768 - Count Control Register (T[0;1;2;3]CTCR - 0 X4000 4070, 0 X4000 8070, 0 X4009 0070, 0 X4009 4070)

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User manual Rev. 3 — 19 December 2013 495 of 841
NXP Semiconductors
UM10360
Chapter 21: LPC176x/5x Timer 0/1/2/3
21.6.3 Count Control Register (T[0/1/2/3]CTCR - 0x4000 4070, 0x4000 8070,
0x4009 0070, 0x4009 4070)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one quarter of
the PCLK clock. Consequently, duration of the high/low levels on the same CAP input in
this case can not be shorter than 1/(2 PCLK).
Table 427. Timer Control Register (TCR, TIMERn: TnTCR - addresses 0x4000 4004, 0x4000 8004, 0x4009 0004,
0x4009 4004) bit description
Bit Symbol Description Reset
Value
0 Counter Enable When one, the Timer Counter and Prescale Counter are enabled for counting. When zero,
the counters are disabled.
0
1 Counter Reset When one, the Timer Counter and the Prescale Counter are synchronously reset on the
next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
0
31:2 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 428. Count Control Register (T[0/1/2/3]CTCR - addresses 0x4000 4070, 0x4000 8070, 0x4009 0070,
0x4009 4070) bit description
Bit Symbol Value Description Reset
Value
1:0 Counter/
Timer
Mode
This field selects which rising PCLK edges can increment the Timer’s Prescale Counter
(PC), or clear the PC and increment the Timer Counter (TC).
00
00 Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale
Register. The Prescale Counter is incremented on every rising PCLK edge.
01 Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
10 Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
11 Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.