UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 464 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
If the I
2
C hardware detects a repeated START condition on the I
2
C-bus before generating
a repeated START condition itself, it will release the bus, and no interrupt request is
generated. If another master frees the bus by generating a STOP condition, the I
2
C block
will transmit a normal START condition (state 0x08), and a retry of the total serial data
transfer can commence.
19.9.7.2 Data transfer after loss of arbitration
Arbitration may be lost in the master transmitter and master receiver modes (see
Figure 91
). Loss of arbitration is indicated by the following states in I2STAT; 0x38, 0x68,
0x78, and 0xB0 (see Figure 93
and Figure 94).
If the STA flag in I2CON is set by the routines which service these states, then, if the bus
is free again, a START condition (state 0x08) is transmitted without intervention by the
CPU, and a retry of the total serial transfer can commence.
19.9.7.3 Forced access to the I
2
C-bus
In some applications, it may be possible for an uncontrolled source to cause a bus
hang-up. In such situations, the problem may be caused by interference, temporary
interruption of the bus or a temporary short-circuit between SDA and SCL.
If an uncontrolled source generates a superfluous START or masks a STOP condition,
then the I
2
C-bus stays busy indefinitely. If the STA flag is set and bus access is not
obtained within a reasonable amount of time, then a forced access to the I
2
C-bus is
possible. This is achieved by setting the STO flag while the STA flag is still set. No STOP
condition is transmitted. The I
2
C hardware behaves as if a STOP condition was received
and is able to transmit a START condition. The STO flag is cleared by hardware
Figure 98
.
19.9.7.4 I
2
C-bus obstructed by a LOW level on SCL or SDA
An I
2
C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on
the bus. If the SCL line is obstructed (pulled LOW) by a device on the bus, no further serial
transfer is possible, and the problem must be resolved by the device that is pulling the
SCL bus line LOW.
Typically, the SDA line may be obstructed by another device on the bus that has become
out of synchronization with the current bus master by either missing a clock, or by sensing
a noise pulse as a clock. In this case, the problem can be solved by transmitting additional
clock pulses on the SCL line Figure 99
. The I
2
C interface does not include a dedicated
time-out timer to detect an obstructed bus, but this can be implemented using another
timer in the system. When detected, software can force clocks (up to 9 may be required)
on SCL until SDA is released by the offending device. At that point, the slave may still be
out of synchronization, so a START should be generated to insure that all I
2
C peripherals
are synchronized.
19.9.7.5 Bus error
A bus error occurs when a START or STOP condition is detected at an illegal position in
the format frame. Examples of illegal positions are during the serial transfer of an address
byte, a data bit, or an acknowledge bit.
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