UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 609 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
1. Read the DMACEnbldChns controller register and find out which channels are
inactive.
2. Choose an inactive channel that has the required priority.
3. Program the DMA controller
31.6.1.6 Halting a DMA channel
Set the halt bit in the relevant DMA channel configuration register. The current source
request is serviced. Any further source DMA request is ignored until the halt bit is cleared.
31.6.1.7 Programming a DMA channel
1. Choose a free DMA channel with the priority needed. DMA channel 0 has the highest
priority and DMA channel 7 the lowest priority.
2. Clear any pending interrupts on the channel to be used by writing to the
DMACIntTCClear and DMACIntErrClear register. The previous channel operation
might have left interrupt active.
3. Write the source address into the DMACCxSrcAddr register.
4. Write the destination address into the DMACCxDestAddr register.
5. Write the address of the next LLI into the DMACCxLLI register. If the transfer
comprises of a single packet of data then 0 must be written into this register.
6. Write the control information into the DMACCxControl register.
7. Write the channel configuration information into the DMACCxConfig register. If the
enable bit is set then the DMA channel is automatically enabled.
31.6.2 Flow control
The device that controls the length of the packet is known as the flow controller. On the
LPC176x/5x, the flow controller is always the DMA Controller, and the packet length is
programmed by software before the DMA channel is enabled.
When the DMA transfer is completed:
1. The DMA Controller issues an acknowledge to the peripheral in order to indicate that
the transfer has finished.
2. A TC interrupt is generated, if enabled.
3. The DMA Controller moves on to the next LLI.
The following sections describe the DMA Controller data flow sequences for the four
allowed transfer types:
• Memory-to-peripheral.
• Peripheral-to-memory.
• Memory-to-memory.
• Peripheral-to-peripheral.
Table 566
indicates the request signals used for each type of transfer.
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