UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 38 of 841
NXP Semiconductors
UM10360
Chapter 4: LPC176x/5x Clocking and power control
feed sequence has been given (see Section 4.5.8 “PLL0 Feed register (PLL0FEED -
0x400F C08C)”).
PLL0 must be set up, enabled, and Lock established before it may be used as a clock
source. When switching from the oscillator clock to the PLL0 output or vice versa, internal
circuitry synchronizes the operation in order to ensure that glitches are not generated.
Hardware does not insure that PLL0 is locked before it is connected or automatically
disconnect PLL0 if lock is lost during operation. In the event of loss of lock on PLL0, it is
likely that the oscillator clock has become unstable and disconnecting PLL0 will not
remedy the situation.
4.5.4 PLL0 Configuration register (PLL0CFG - 0x400F C084)
The PLL0CFG register contains PLL0 multiplier and divider values. Changes to the
PLL0CFG register do not take effect until a correct PLL feed sequence has been given
(see Section 4.5.8 “
PLL0 Feed register (PLL0FEED - 0x400F C08C)”). Calculations for
the PLL frequency, and multiplier and divider values are found in the Section 4.5.10 “
PLL0
frequency calculation”.
Table 19. PLL Control register (PLL0CON - address 0x400F C080) bit description
Bit Symbol Description Reset
value
0 PLLE0 PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate
PLL0 and allow it to lock to the requested frequency. See PLL0STAT
register, Table 22
.
0
1 PLLC0 PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and
locked, then followed by a valid PLL0 feed sequence causes PLL0 to
become the clock source for the CPU, AHB peripherals, and used to
derive the clocks for APB peripherals. The PLL0 output may potentially
be used to clock the USB subsystem if the frequency is 48 MHz. See
PLL0STAT register, Table 22
.
0
31:2 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
Table 20. PLL0 Configuration register (PLL0CFG - address 0x400F C084) bit description
Bit Symbol Description Reset
value
14:0 MSEL0 PLL0 Multiplier value. Supplies the value "M" in PLL0 frequency
calculations. The value stored here is M - 1. Supported values for M
are 6 through 512 and those listed in Table 21
.
Note: Not all values of M are needed, and therefore some are not
supported by hardware. For details on selecting values for MSEL0 see
Section 4.5.10 “
PLL0 frequency calculation”.
0
15 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
23:16 NSEL0 PLL0 Pre-Divider value. Supplies the value "N" in PLL0 frequency
calculations. The value stored here is N - 1. Supported values for N are
1 through 32.
Note: For details on selecting the right value for NSEL0 see
Section 4.5.10 “
PLL0 frequency calculation”.
0
31:24 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
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