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NXP Semiconductors LPC1768 - DMA Interrupt Status Register (Dmacintstat - 0 X5000 4000); DMA Interrupt Terminal Count Request Status Register (Dmacinttcstat - 0 X5000 4004); DMA Interrupt Terminal Count Request Clear Register (Dmacinttcclear - 0 X5000 4008); DMA Interrupt Error Status Register (Dmacinterrstat - 0 X5000 400 C)

NXP Semiconductors LPC1768
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UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 596 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.5.1 DMA Interrupt Status register (DMACIntStat - 0x5000 4000)
The DMACIntStat Register is read-only and shows the status of the interrupts after
masking. A 1 bit indicates that a specific DMA channel interrupt request is active. The
request can be generated from either the error or terminal count interrupt requests.
Table 545
shows the bit assignments of the DMACIntStat Register.
31.5.2 DMA Interrupt Terminal Count Request Status register
(DMACIntTCStat - 0x5000 4004)
The DMACIntTCStat Register is read-only and indicates the status of the terminal count
after masking. Table 546
shows the bit assignments of the DMACIntTCStat Register.
31.5.3 DMA Interrupt Terminal Count Request Clear register
(DMACIntTCClear - 0x5000 4008)
The DMACIntTCClear Register is write-only and clears one or more terminal count
interrupt requests. When writing to this register, each data bit that contains a 1 causes the
corresponding bit in the status register (DMACIntTCStat) to be cleared. Data bits that are
0 have no effect. Table 547
shows the bit assignments of the DMACIntTCClear Register.
31.5.4 DMA Interrupt Error Status register (DMACIntErrStat - 0x5000 400C)
The DMACIntErrStat Register is read-only and indicates the status of the error request
after masking. Table 548
shows the bit assignments of the DMACIntErrStat Register.
Table 545. DMA Interrupt Status register (DMACIntStat - 0x5000 4000)
Bit Name Function
7:0 IntStat Status of DMA channel interrupts after masking. Each bit represents one channel:
0 - the corresponding channel has no active interrupt request.
1 - the corresponding channel does have an active interrupt request.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 546. DMA Interrupt Terminal Count Request Status register (DMACIntTCStat - 0x5000 4004)
Bit Name Function
7:0 IntTCStat Terminal count interrupt request status for DMA channels. Each bit represents one
channel:
0 - the corresponding channel has no active terminal count interrupt request.
1 - the corresponding channel does have an active terminal count interrupt request.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 547. DMA Interrupt Terminal Count Request Clear register (DMACIntTCClear - 0x5000 4008)
Bit Name Function
7:0 IntTCClear Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels.
Each bit represents one channel:
0 - writing 0 has no effect.
1 - clears the corresponding channel terminal count interrupt.
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.

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