NXP Semiconductors LPC1768 - Features; Architecture; Interfaces

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User manual Rev. 3 — 19 December 2013 271 of 841
NXP Semiconductors
UM10360
Chapter 12: LPC176x/5x USB Host controller
12.3.1 Features
• OHCI compliant.
• OpenHCI specifies the operation and interface of the USB Host Controller and SW
Driver
– USBOperational: Process Lists and generate SOF Tokens.
– USBReset: Forces reset signaling on the bus, SOF disabled.
– USBSuspend: Monitor USB for wake-up activity.
– USBResume: Forces resume signaling on the bus.
• The Host Controller has four USB states visible to the SW Driver.
• HCCA register points to Interrupt and Isochronous Descriptors List.
• ControlHeadED and BulkHeadED registers point to Control and Bulk Descriptors List.
12.3.2 Architecture
The architecture of the USB host controller is shown below in Figure 33.
12.4 Interfaces
The USB interface is controlled by the OTG controller. It has one USB port.
LS Low Speed
OHCI Open Host Controller Interface
USB Universal Serial Bus
Table 252. USB (OHCI) related acronyms and abbreviations used in this chapter …continued
Acronym/abbreviation Description
Fig 33. USB Host controller block diagram
REGISTER
INTERFACE
BUS
MASTER
INTERFACE
USB
ATX
DMA interface
(AHB master)
register
interface
(AHB slave)
AHB bus
HOST
CONTROLLER
ATX
CONTROL
LOGIC/
PORT
MUX
USB
port
USB HOST BLOCK