NXP Semiconductors LPC1768 - C308)

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 285 of 841
NXP Semiconductors
UM10360
Chapter 13: LPC176x/5x USB OTG
13.8.13 I
2
C Control Register (I2C_CTL - 0x5000 C308)
The I2C_CTL register is used to enable interrupts and reset the I
2
C state machine.
Enabled interrupts cause the USB_I2C_INT interrupt output line to be asserted when set.
11 TFE Transmit FIFO Empty. TFE is set when the TX FIFO is empty
and is cleared when the TX FIFO contains valid data.
1
0 TX FIFO contains valid data.
1 TX FIFO is empty
31:12 - NA Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
NA
Table 265. I
2
C status register (I2C_STS - address 0x5000 C304) bit description …continued
Bit Symbol Value Description Reset
Value
Table 266. I
2
C Control register (I2C_CTL - address 0x5000 C308) bit description
Bit Symbol Value Description Reset
Value
0 TDIE Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I
2
C
issued a STOP condition.
0
0 Disable the TDI interrupt.
1 Enable the TDI interrupt.
1 AFIE Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is
asserted during transmission when trying to set SDA high, but the bus is driven low by
another device.
0
0 Disable the AFI.
1 Enable the AFI.
2 NAIE Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling
that transmitted byte was not acknowledged.
0
0 Disable the NAI.
1 Enable the NAI.
3 DRMIE Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which
signals that the master transmitter has run out of data, has not issued a STOP, and is
holding the SCL line low.
0
0 Disable the DRMI interrupt.
1 Enable the DRMI interrupt.
4 DRSIE Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which
signals that the slave transmitter has run out of data and the last byte was acknowledged,
so the SCL line is being held low.
0
0 Disable the DRSI interrupt.
1 Enable the DRSI interrupt.
5 REFIE Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to
indicate that the receive FIFO cannot accept any more data.
0
0 Disable the RFFI.
1 Enable the RFFI.