UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 757 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.3.5 Power management
Note: NXP devices based on the Cortex-M3 processor, including the LPC176x/5x,
support additional reduced power modes. See Section 4.8 “
Power control” for
information on all available reduced power modes.
The Cortex-M3 processor sleep modes reduce power consumption:
• Sleep mode stops the processor clock
• Deep sleep mode stops the system clock and switches off the PLL and flash memory.
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see Section 34.4.3.7
“System Control Register”. For more information about the behavior of the sleep modes
see Section 4.8 “
Power control”.
This section describes the mechanisms for entering sleep mode, and the conditions for
waking up from sleep mode.
34.3.5.1 Entering sleep mode
This section describes the mechanisms software can use to put the processor into sleep
mode.
The system can generate spurious wakeup events, for example a debug operation wakes
up the processor. Therefore software must be able to put the processor back into sleep
mode after such an event. A program might have an idle loop to put the processor back to
sleep mode.
34.3.5.1.1 Wait for interrupt
The wait for interrupt instruction,
WFI
, causes immediate entry to sleep mode. When the
processor executes a
WFI
instruction it stops executing instructions and enters sleep
mode. See Section 34.2.10.12 “
WFI” for more information.
34.3.5.1.2 Wait for event
Note: LPC176x/5x devices based on the Cortex-M3 processor do not implement
external events.
The wait for event instruction,
WFE
, causes entry to sleep mode conditional on the value of
an one-bit event register. When the processor executes a
WFE
instruction, it checks this
register:
• if the register is 0 the processor stops executing instructions and enters sleep mode
• if the register is 1 the processor clears the register to 0 and continues executing
instructions without entering sleep mode.
See Section 34.2.10.11 “
WFE” for more information.
If the event register is 1, this indicate that the processor must not enter sleep mode on
execution of a
WFE
instruction. Typically, this is because an external event signal is
asserted, or a processor in the system has executed an
SEV
instruction, see
Section 34.2.10.9 “
SEV”. Software cannot access this register directly.
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