UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 122 of 841
NXP Semiconductors
UM10360
Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO)
• Registers provide a software view of pending rising edge interrupts, pending falling
edge interrupts, and overall pending GPIO interrupts.
• GPIO0 and GPIO2 interrupts share the same position in the NVIC with External
Interrupt 3.
9.3 Applications
• General purpose I/O
• Driving LEDs or other indicators
• Controlling off-chip devices
• Sensing digital inputs, detecting edges
• Bringing the part out of Power-down mode
9.4 Pin description
[1] P0[14:12] are not available.
[2] P1[2], P1[3], P1[7:5], P1[13:11] are not available.
Table 100. GPIO pin description
Pin Name Type Description
P0[30:0]
[1]
;
P1[31:0]
[2]
;
P2[13:0];
P3[26:25];
P4[29:28]
Input/
Output
General purpose input/output. These are typically shared with other
peripherals functions and will therefore not all be available in an
application. Packaging options may affect the number of GPIOs
available in a particular device.
Some pins may be limited by requirements of the alternate functions of
the pin. For example, the pins containing the I
2
C0 functions are
open-drain for any function selected on that pin. Details may be found
in Section 7.1.1
.
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