UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 270 of 841
12.1 How to read this chapter
The USB host controller is available on the LPC1768, LPC1766, LPC1765, LPC1758,
LPC1756, and LPC1754. On these devices, the USB controller can be configured for
device, Host, or OTG operation.
12.2 Basic configuration
The USB controller is configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bit PCUSB.
Remark: On reset, the USB block is disabled (PCUSB = 0).
2. Clock: The USB block can be used with a dedicated USB PLL (PLL1) to obtain the
USB clock or with the Main PLL (PLL0). See Section 4.6.1
.
3. Pins: Select USB pins and their modes in PINSEL0 to PINSEL5 and PINMODE0 to
PINMODE5 (Section 8.5
).
4. Wake-up: Activity on the USB bus port can wake up the microcontroller from
Power-down mode, see Section 4.8.8
.
5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
6. Initialization: see Section 13.11
.
12.3 Introduction
This section describes the host portion of the USB 2.0 OTG dual role core which
integrates the host controller (OHCI compliant), device controller, and I
2
C interface. The
I
2
C interface controls the external OTG ATX.
The USB is a 4 wire bus that supports communication between a host and a number (127
max.) of peripherals. The host controller allocates the USB bandwidth to attached devices
through a token based protocol. The bus supports hot plugging, un-plugging and dynamic
configuration of the devices. All transactions are initiated by the host controller.
The host controller enables data exchange with various USB devices attached to the bus.
It consists of register interface, serial interface engine and DMA controller. The register
interface complies to the OHCI specification.
UM10360
Chapter 12: LPC176x/5x USB Host controller
Rev. 3 — 19 December 2013 User manual
Table 252. USB (OHCI) related acronyms and abbreviations used in this chapter
Acronym/abbreviation Description
AHB Advanced High-Performance Bus
ATX Analog Transceiver
DMA Direct Memory Access
FS Full Speed
To Next Page
Loading...
Need help?
General
