UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 622 of 841
NXP Semiconductors
UM10360
Chapter 32: LPC176x/5x Flash memory interface and programming
32.6 Code Read Protection (CRP)
Code Read Protection is a mechanism that allows user to enable different levels of
security in the system so that access to the on-chip flash and use of the ISP can be
restricted. When needed, CRP is invoked by programming a specific pattern in flash
location at 0x000002FC. IAP commands are not affected by the code read protection.
Important: Any CRP change becomes effective only after the device has gone
through a power cycle.
[1] CRP is supported by all LPC176x/5x parts with the exception of part LPC1751 with
partID 0x2500 1110. Part LPC1751 with partID 0x2500 1118 supports all three CRP
levels (see Errata note).
Table 568. Code Read Protection options
[1]
Name Pattern
programmed in
0x000002FC
Description
CRP1 0x12345678 Access to chip via the JTAG pins is disabled. This mode allows partial
flash update using the following ISP commands and restrictions:
• Write to RAM command can not access RAM below 0x10000200.
This is due to use of the RAM by the ISP code, see
Section 32.3.2.7
.
• Read Memory command: disabled.
• Copy RAM to Flash command: cannot write to Sector 0.
• Go command: disabled.
• Erase sector(s) command: can erase any individual sector except
sector 0 only, or can erase all sectors at once.
• Compare command: disabled
This mode is useful when CRP is required and flash field updates are
needed but all sectors can not be erased. The compare command is
disabled, so in the case of partial flash updates the secondary loader
should implement a checksum mechanism to verify the integrity of the
flash.
CRP2 0x87654321 This is similar to CRP1 with the following additions:
• Write to RAM command: disabled.
• Copy RAM to Flash: disabled.
• Erase command: only allows erase of all sectors.
CRP3 0x43218765 This is similar to CRP2, but ISP entry by pulling P2.10 LOW is
disabled if a valid user code is present in flash sector 0.
This mode effectively disables ISP override using the P2.10 pin. It is
up to the user’s application to provide for flash updates by using IAP
calls or by invoking ISP with UART0.
Caution: If CRP3 is selected, no future factory testing can be
performed on the device.
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