UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 441 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
[1] Reset value reflects the data stored in used bits only. It does not include reserved bits content.
19.8.1 I
2
C Control Set register (I2CONSET: I
2
C0, I2C0CONSET -
0x4001 C000; I
2
C1, I2C1CONSET - 0x4005 C000; I
2
C2, I2C2CONSET -
0x400A 0000)
The I2CONSET registers control setting of bits in the I2CON register that controls
operation of the I
2
C interface. Writing a one to a bit of this register causes the
corresponding bit in the I
2
C control register to be set. Writing a zero has no effect.
Reading this register provides the current values of the control and flag bits.
I2ADR2 I2C Slave Address Register 2. Contains the 7-bit
slave address for operation of the I
2
C interface in
slave mode, and is not used in master mode. The
least significant bit determines whether a slave
responds to the General Call address.
R/W 0x00 I2C0ADR2 - 0x4001 C024
I2C1ADR2 - 0x4005 C024
I2C2ADR2 - 0x400A 0024
I2ADR3
I2C Slave Address Register 3. Contains the 7-bit
slave address for operation of the I
2
C interface in
slave mode, and is not used in master mode. The
least significant bit determines whether a slave
responds to the General Call address.
R/W 0x00 I2C0ADR3 - 0x4001 C028
I2C1ADR3 - 0x4005 C028
I2C2ADR3 - 0x400A 0028
I2DATA_
BUFFER
Data buffer register. The contents of the 8 MSBs of
the I2DAT shift register will be transferred to the
I2DATA_BUFFER automatically after every 9 bits (8
bits of data plus ACK or NACK) has been received
on the bus.
RO 0x00 I2C0DATA_ BUFFER - 0x4001 C02C
I2C1DATA_ BUFFER - 0x4005 C02C
I2C2DATA_ BUFFER - 0x400A 002C
I2MASK0
I2C Slave address mask register 0. This mask
register is associated with I2ADR0 to determine an
address match. The mask register has no effect
when comparing to the General Call address
(‘0000000’).
R/W 0x00 I2C0MASK0 - 0x4001 C030
I2C1MASK0 - 0x4005 C030
I2C2MASK0 - 0x400A 0030
I2MASK1
I2C Slave address mask register 1. This mask
register is associated with I2ADR0 to determine an
address match. The mask register has no effect
when comparing to the General Call address
(‘0000000’).
R/W 0x00 I2C0MASK1 - 0x4001 C034
I2C1MASK1 - 0x4005 C034
I2C2MASK1 - 0x400A 0034
I2MASK2
I2C Slave address mask register 2. This mask
register is associated with I2ADR0 to determine an
address match. The mask register has no effect
when comparing to the General Call address
(‘0000000’).
R/W 0x00 I2C0MASK2 - 0x4001 C038
I2C1MASK2 - 0x4005 C038
I2C2MASK2 - 0x400A 0038
I2MASK3
I2C Slave address mask register 3. This mask
register is associated with I2ADR0 to determine an
address match. The mask register has no effect
when comparing to the General Call address
(‘0000000’).
R/W 0x00 I2C0MASK3 - 0x4001 C03C
I2C1MASK3 - 0x4005 C03C
I2C2MASK3 - 0x400A 003C
Table 383. I
2
C register map
Generic
Name
Description Access Reset
value
[1]
I
2
Cn Name & Address
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