UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 314 of 841
NXP Semiconductors
UM10360
Chapter 14: LPC176x/5x UART0/2/3
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART0/2/3 disabled making sure that
UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this
feature.
UART0/2/3 baud rate can be calculated as (n = 0/2/3):
(4)
Where PCLK is the peripheral clock, U0/2/3DLM and U0/2/3DLL are the standard
UART0/2/3 baud rate divider registers, and DIVADDVAL and MULVAL are UART0/2/3
fractional baud rate generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
1. 1 ï‚£ MULVAL ï‚£ 15
2. 0 ï‚£ DIVADDVAL ï‚£ 14
3. DIVADDVAL < MULVAL
The value of the U0/2/3FDR should not be modified while transmitting/receiving data or
data may be lost or corrupted.
If the U0/2/3FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
14.4.12.1 Baud rate calculation
UARTn can operate with or without using the Fractional Divider. In real-life applications it
is likely that the desired baud rate can be achieved using several different Fractional
Divider settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baud rate with a
relative error of less than 1.1% from the desired one.
UARTn
baudrate
PCLK
16 256 UnDLM UnDLL+ 1
DivAddVal
MulVal
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+


ï‚´
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