UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 489 of 841
NXP Semiconductors
UM10360
Chapter 20: LPC176x/5x I2S
20.8 FIFO controller
Handling of data for transmission and reception is performed via the FIFO controller which
can generate two DMA requests and an interrupt request. The controller consists of a set
of comparators which compare FIFO levels with depth settings contained in registers. The
current status of the level comparators can be seen in the APB status register.
System signaling occurs when a level detection is true and enabled.
Fig 112. 4-wire receiver slave mode sharing the transmitter bit clock and WS
I2SRX_WS
I2SRX_SDA
TX bit clock
TX_WS ref
I
2
S
peripheral
block
(receive)
Table 421. Conditions for FIFO level comparison
Level Comparison Condition
dmareq_tx_1 tx_depth_dma1 >= tx_level
dmareq_rx_1 rx_depth_dma1 <= rx_level
dmareq_tx_2 tx_depth_dma2 >= tx_level
dmareq_rx_2 rx_depth_dma2 <= rx_level
irq_tx tx_depth_irq >= tx_level
irq_rx rx_depth_irq <= rx_level
Table 422. DMA and interrupt request generation
System Signaling Condition
irq (irq_rx & rx_irq_enable) | (irq_tx & tx_irq_enable)
dmareq[0] (dmareq_tx_1 & tx_dma1_enable ) | (dmareq_rx_1 &
rx_dma1_enable )
dmareq[1] ( dmareq_tx_2 & tx_dma2_enable ) | (dmareq_rx_2 &
rx_dma2_enable )
Table 423. Status feedback in the I2SSTATE register
Status Feedback Status
irq irq_rx | irq_tx
dmareq1 (dmareq_tx_1 | dmareq_rx_1)
dmareq2 (dmareq_rx_2 | dmareq_tx_2)
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