UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 258 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
[1] Write-only in ATLE mode
Legend: R - Read; W - Write; I - Initialize
11.15.4.1 Next_DD_pointer
Pointer to the memory location from where the next DMA descriptor will be fetched.
11.15.4.2 DMA_mode
Specifies the DMA mode of operation. Two modes have been defined: Normal and
Automatic Transfer Length Extraction (ATLE) mode. In normal mode, software initializes
the DMA_buffer_length for OUT endpoints. In ATLE mode, the DMA_buffer_length is
extracted from the incoming data. See Section 11.15.7 “
Auto Length Transfer Extraction
(ATLE) mode operation” on page 264 for more details.
11.15.4.3 Next_DD_valid
This bit indicates whether the software has prepared the next DMA descriptor. If set, the
DMA engine fetches the new descriptor when it is finished with the current one.
1 R R/W 1:0 DMA_mode (00 -Normal; 01 - ATLE)
R R/W 2 Next_DD_valid (1 - valid; 0 - invalid)
--3Reserved
R R/W 4 Isochronous_endpoint (1 - isochronous; 0 - non-isochronous)
R R/W 15:5 Max_packet_size
R/W
[1]
R/W 31:16 DMA_buffer_length
This value is specified in bytes for non-isochronous endpoints and in
number of packets for isochronous endpoints.
2 R/W R/W 31:0 DMA_buffer_start_addr
3 R/W R/I 0 DD_retired (To be initialized to 0)
W R/I 4:1 DD_status (To be initialized to 0000):
0000 - NotServiced
0001 - BeingServiced
0010 - NormalCompletion
0011 - DataUnderrun (short packet)
1000 - DataOverrun
1001 - SystemError
W R/I 5 Packet_valid (To be initialized to 0)
W R/I 6 LS_byte_extracted (ATLE mode) (To be initialized to 0)
W R/I 7 MS_byte_extracted (ATLE mode) (To be initialized to 0)
R W 13:8 Message_length_position (ATLE mode)
- - 15:14 Reserved
R/W R/I 31:16 Present_DMA_count (To be initialized to 0)
4 R/W R/W 31:0 Isochronous_packetsize_memory_address
Table 251. DMA descriptor
Word
position
Access
(H/W)
Access
(S/W)
Bit
position
Description
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