UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 344 of 841
16.1 Basic configuration
The CAN1/2 peripherals are configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bits PCAN1/2.
Remark: On reset, the CAN1/2 blocks are disabled (PCAN1/2 = 0).
2. Peripheral clock: In the PCLKSEL0 register (Table 40
), select PCLK_CAN1,
PCLK_CAN2, and, for the acceptance filter, PCLK_ACF. Note that these must all be
the same value.
Remark: If CAN baud rates above 100 kbit/s (see Table 322
) are needed, do not
select the IRC as the clock source (see Table 17
).
3. Wake-up: CAN controllers are able to wake up the microcontroller from Power-down
mode, see Section 4.8.8
.
4. Pins: Select CAN1/2 pins through the PINSEL registers and their pin modes through
the PINMODE registers (Section 8.5
).
5. Interrupts: CAN interrupts are enabled using the CAN1/2IER registers (Table 321
).
Interrupts are enabled in the NVIC using the appropriate Interrupt Set Enable register.
6. CAN controller initialization: see CANMOD register (Section 16.7.1
).
16.2 CAN controllers
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The CAN Controller is designed to provide a full
implementation of the CAN-Protocol according to the CAN Specification Version 2.0B.
Microcontrollers with this on-chip CAN controller are used to build powerful local networks
by supporting distributed real-time control with a very high level of security. The
applications are automotive, industrial environments, and high speed networks as well as
low cost multiplex wiring. The result is a strongly reduced wiring harness and enhanced
diagnostic and supervisory capabilities.
The CAN block is intended to support multiple CAN buses simultaneously, allowing the
device to be used as a gateway, switch, or router among a number of CAN buses in
various applications.
The CAN module consists of two elements: the controller and the Acceptance Filter. All
registers and the RAM are accessed as 32-bit words.
16.3 Features
16.3.1 General CAN features
• Compatible with CAN specification 2.0B, ISO 11898-1.
• Multi-master architecture with non destructive bit-wise arbitration.
• Bus access priority determined by the message identifier (11-bit or 29-bit).
UM10360
Chapter 16: LPC176x/5x CAN1/2
Rev. 3 — 19 December 2013 User manual
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