NXP Semiconductors LPC1768 - Interrupt Register (T[0;1;2;3]IR - 0 X4000 4000, 0 X4000 8000, 0 X4009 0000, 0 X4009 4000); Timer Control Register; 0 X4000 4004, 0 X4000 8004, 0 X4009 0004, 0 X4009 4004)

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 494 of 841
NXP Semiconductors
UM10360
Chapter 21: LPC176x/5x Timer 0/1/2/3
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
21.6.1 Interrupt Register (T[0/1/2/3]IR - 0x4000 4000, 0x4000 8000,
0x4009 0000, 0x4009 4000)
The Interrupt Register consists of 4 bits for the match interrupts and 4 bits for the capture
interrupts. If an interrupt is generated then the corresponding bit in the IR will be high.
Otherwise, the bit will be low. Writing a logic one to the corresponding IR bit will reset the
interrupt. Writing a zero has no effect. The act of clearing an interrupt for a timer match
also clears any corresponding DMA request.
21.6.2 Timer Control Register (T[0/1/2/3]CR - 0x4000 4004, 0x4000 8004,
0x4009 0004, 0x4009 4004)
The Timer Control Register (TCR) is used to control the operation of the Timer/Counter.
CR0 Capture Register 0. CR0 is loaded with the value of TC when there
is an event on the CAPn.0(CAP0.0 or CAP1.0 respectively) input.
RO 0 T0CR0 - 0x4000 402C
T1CR0 - 0x4000 802C
T2CR0 - 0x4009 002C
T3CR0 - 0x4009 402C
CR1 Capture Register 1. See CR0 description. RO 0 T0CR1 - 0x4000 4030
T1CR1 - 0x4000 8030
T2CR1 - 0x4009 0030
T3CR1 - 0x4009 4030
EMR External Match Register. The EMR controls the external match pins
MATn.0-3 (MAT0.0-3 and MAT1.0-3 respectively).
R/W 0 T0EMR - 0x4000 403C
T1EMR - 0x4000 803C
T2EMR - 0x4009 003C
T3EMR - 0x4009 403C
CTCR Count Control Register. The CTCR selects between Timer and
Counter mode, and in Counter mode selects the signal and edge(s)
for counting.
R/W 0 T0CTCR - 0x4000 4070
T1CTCR - 0x4000 8070
T2CTCR - 0x4009 0070
T3CTCR - 0x4009 4070
Table 425. TIMER/COUNTER0-3 register map …continued
Generic
Name
Description Access Reset
Value
[1]
TIMERn Register/
Name & Address
Table 426. Interrupt Register (T[0/1/2/3]IR - addresses 0x4000 4000, 0x4000 8000, 0x4009 0000, 0x4009 4000) bit
description
Bit Symbol Description Reset
Value
0 MR0 Interrupt Interrupt flag for match channel 0. 0
1 MR1 Interrupt Interrupt flag for match channel 1. 0
2 MR2 Interrupt Interrupt flag for match channel 2. 0
3 MR3 Interrupt Interrupt flag for match channel 3. 0
4 CR0 Interrupt Interrupt flag for capture channel 0 event. 0
5 CR1 Interrupt Interrupt flag for capture channel 1 event. 0
31:6 - Reserved -