UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 519 of 841
NXP Semiconductors
UM10360
Chapter 24: LPC176x/5x Pulse Width Modulator (PWM)
24.6.5 PWM Capture Control Register (PWM1CCR - 0x4001 8028)
The Capture Control Register is used to control whether one of the four Capture Registers
is loaded with the value in the Timer Counter when a capture event occurs, and whether
an interrupt is generated by the capture event. Setting both the rising and falling bits at the
same time is a valid configuration, resulting in a capture event for both edges. In the
descriptions below, “n” represents the Timer number, 0 or 1.
8 PWMMR2S 1 Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR2 matches the PWMTC.
0
0 This feature is disabled
9 PWMMR3I 1 Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in
the PWMTC.
0
0 This interrupt is disabled.
10 PWMMR3R 1 Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it. 0
0 This feature is disabled
11 PWMMR3S 1 Stop on PWMMR3: The PWMTC and PWMPC will be stopped and PWMTCR[0] will
be set to 0 if PWMMR3 matches the PWMTC.
0
0 This feature is disabled
12 PWMMR4I 1 Interrupt on PWMMR4: An interrupt is generated when PWMMR4 matches the value
in the PWMTC.
0
0 This interrupt is disabled.
13 PWMMR4R 1 Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it. 0
0 This feature is disabled.
14 PWMMR4S 1 Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR4 matches the PWMTC.
0
0 This feature is disabled
15 PWMMR5I 1 Interrupt on PWMMR5: An interrupt is generated when PWMMR5 matches the value
in the PWMTC.
0
0 This interrupt is disabled.
16 PWMMR5R 1 Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it. 0
0 This feature is disabled.
17 PWMMR5S 1 Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR5 matches the PWMTC.
0
0 This feature is disabled
18 PWMMR6I 1 Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in
the PWMTC.
0
0 This interrupt is disabled.
19 PWMMR6R 1 Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it. 0
0 This feature is disabled.
20 PWMMR6S 1 Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR[0] will be
set to 0 if PWMMR6 matches the PWMTC.
0
31:21 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 449: Match Control Register (PWM1MCR - address 0x4001 8014) bit description …continued
Bit Symbol Value Description Reset
Value
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