UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 25 of 841
NXP Semiconductors
UM10360
Chapter 3: LPC176x/5x System control
3.6.1 Register description
The external interrupt function has four registers associated with it. The EXTINT register
contains the interrupt flags. The EXTMODE and EXTPOLAR registers specify the level
and edge sensitivity parameters.
[1] Reset Value reflects the data stored in used bits only. It does not include reserved bits content.
3.6.2 External Interrupt flag register (EXTINT - 0x400F C140)
When a pin is selected for its external interrupt function, the level or edge on that pin
(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in
this register. This asserts the corresponding interrupt request to the NVIC, which will
cause an interrupt if interrupts from the pin are enabled.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding
bits. In level-sensitive mode the interrupt is cleared only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wake-up and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
event that was just triggered by activity on the EINT pin will not be recognized in future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt), the
corresponding bit in the EXTINT register must be cleared! For details see
Section 3.6.3 “
External Interrupt Mode register (EXTMODE - 0x400F C148)” and
Section 3.6.4 “
External Interrupt Polarity register (EXTPOLAR - 0x400F C14C)”.
For example, if a system wakes up from Power-down using low level on external interrupt
0 pin, its post wake-up code must reset EINT0 bit in order to allow future entry into the
Power-down mode. If EINT0 bit is left set to 1, subsequent attempt(s) to invoke
Power-down mode will fail. The same goes for external interrupt handling.
More details on Power-down mode will be discussed in the following chapters.
Table 9. External Interrupt registers
Name Description Access Reset
value
[1]
Address
EXTINT The External Interrupt Flag Register contains
interrupt flags for EINT0, EINT1, EINT2 and
EINT3. See Table 10
.
R/W 0x00 0x400F C140
EXTMODE The External Interrupt Mode Register controls
whether each pin is edge- or level-sensitive.
See Table 11
.
R/W 0x00 0x400F C148
EXTPOLAR The External Interrupt Polarity Register controls
which level or edge on each pin will cause an
interrupt. See Table 12
.
R/W 0x00 0x400F C14C
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