UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 531 of 841
NXP Semiconductors
UM10360
Chapter 25: LPC176x/5x Motor control PWM
25.7.3.2 MCPWM Interrupt Enable set address (MCINTEN_SET - 0x400B 8054)
Writing ones to this write-only address sets the corresponding bits in MCINTEN, thus
enabling interrupts.
25.7.3.3 MCPWM Interrupt Enable clear address (MCINTEN_CLR - 0x400B 8058)
Writing ones to this write-only address clears the corresponding bits in MCINTEN, thus
disabling interrupts.
25.7.3.4 MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068)
The MCINTF register includes all MCPWM interrupt flags, which are set when the
corresponding hardware event occurs, or when ones are written to the MCINTF_SET
address. When corresponding bits in this register and MCINTEN are both 1, the MCPWM
asserts its interrupt request to the Interrupt Controller module. This address is read-only,
but the bits in the underlying register can be modified by writing ones to addresses
MCINTF_SET and MCINTF_CLR.
25.7.3.5 MCPWM Interrupt Flags set address (MCINTF_SET - 0x400B 806C)
Writing one(s) to this write-only address sets the corresponding bit(s) in MCINTF, thus
possibly simulating hardware interrupt(s).
25.7.3.6 MCPWM Interrupt Flags clear address (MCINTF_CLR - 0x400B 8070)
Writing one(s) to this write-only address sets the corresponding bit(s) in MCINTF, thus
clearing the corresponding interrupt request(s). This is typically done in interrupt service
routines.
Table 464. PWM interrupt enable set register (MCINTEN_SET - address 0x400B 8054) bit
description
Bit Description
31:0 Writing ones to this address sets the corresponding bits in MCINTEN, thus enabling
interrupts. See Table 462
.
Table 465. PWM interrupt enable clear register (MCINTEN_CLR - address 0x400B 8058) bit
description
Bit Description
31:0 Writing ones to this address clears the corresponding bits in MCINTEN, thus disabling
interrupts. See Table 462
.
Table 466. MCPWM Interrupt Flags read address (MCINTF - 0x400B 8068) bit description
Bit Value Description Reset
value
31:0 See Table 462 for the bit allocation. 0
1 If the corresponding bit in MCINTEN is 1, the MCPWM module is asserting its interrupt request to
the Interrupt Controller.
0 This interrupt source is not contributing to the MCPWM interrupt request.
Table 467. MCPWM Interrupt Flags set address (PWMINTF_SET - 0x400B 806C) bit
description
Bit Description
31:0 Writing one(s) to this write-only address sets the corresponding bit(s) in the MCINTF
register, thus possibly simulating hardware interrupt(s). See Table 462
.
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