UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 5 of 841
NXP Semiconductors
UM10360
Chapter 1: LPC176x/5x Introductory information
1.2 Features
Refer to Section 1.4.1 for details of features on specific part numbers.
• ARM Cortex-M3 processor, running at frequencies of up to 120 MHz on high speed
versions (LPC1769 and LPC1759), up to 100 MHz on other versions. A Memory
Protection Unit (MPU) supporting eight regions is included.
• ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC).
• Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and
In-Application Programming (IAP) capabilities. The combination of an enhanced flash
memory accelerator and location of the flash memory on the CPU local code/data bus
provides high code performance from flash.
• Up to 64 kB on-chip SRAM includes:
– Up to 32 kB of SRAM on the CPU with local code/data bus for high-performance
CPU access.
– Up to two 16 kB SRAM blocks with separate access paths for higher throughput.
These SRAM blocks may be used for Ethernet, USB, and DMA memory, as well as
for general purpose instruction and data storage.
• Eight channel General Purpose DMA controller (GPDMA) on the AHB multilayer
matrix that can be used with the SSP, I
2
S, UART, the Analog-to-Digital and
Digital-to-Analog converter peripherals, timer match signals, GPIO, and for
memory-to-memory transfers.
• Multilayer AHB matrix interconnect provides a separate bus for each AHB master.
AHB masters include the CPU, General Purpose DMA controller, Ethernet MAC, and
the USB interface. This interconnect provides communication with no arbitration
delays unless two masters attempt to access the same slave at the same time.
• Split APB bus allows for higher throughput with fewer stalls between the CPU and
DMA. A single level of write buffering allows the CPU to continue without waiting for
completion of APB writes if the APB was not already busy.
• Serial interfaces:
– Ethernet MAC with RMII interface and dedicated DMA controller.
– USB 2.0 full-speed controller that can be configured for either device, Host, or
OTG operation with an on-chip PHY for device and Host functions and a dedicated
DMA controller.
– Four UARTs with fractional baud rate generation, internal FIFO, IrDA, and DMA
support. One UART has modem control I/O and RS-485/EIA-485 support.
– Two-channel CAN controller.
– Two SSP controllers with FIFO and multi-protocol capabilities. The SSP interfaces
can be used with the GPDMA controller.
– SPI controller with synchronous, serial, full duplex communication and
programmable data length. SPI is included as a legacy peripheral and can be used
instead of SSP0.
– Three enhanced I
2
C-bus interfaces, one with an open-drain output supporting the
full I
2
C specification and Fast mode plus with data rates of 1Mbit/s, two with
standard port pins. Enhancements include multiple address recognition and
monitor mode.
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