NXP Semiconductors LPC1768 - GPIO Port Pin Value Register Fioxpin (FIO0 PIN to FIO4 PIN- 0 X2009 C014 to 0 X2009 C094)

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User manual Rev. 3 — 19 December 2013 128 of 841
NXP Semiconductors
UM10360
Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO)
9.5.4 GPIO port Pin value register FIOxPIN (FIO0PIN to FIO4PIN- 0x2009
C014 to 0x2009 C094)
This register provides the value of port pins that are configured to perform only digital
functions. The register will give the logic value of the pin regardless of whether the pin is
configured for input or output, or as GPIO or an alternate digital function. As an example,
a particular port pin may have GPIO input, GPIO output, UART receive, and PWM output
as selectable functions. Any configuration of that pin will allow its current logic state to be
read from the corresponding FIOxPIN register.
If a pin has an analog function as one of its options, the pin state cannot be read if the
analog configuration is selected. Selecting the pin as an A/D input disconnects the digital
features of the pin. In that case, the pin value read in the FIOxPIN register is not valid.
Writing to the FIOxPIN register stores the value in the port output register, bypassing the
need to use both the FIOxSET and FIOxCLR registers to obtain the entire written value.
This feature should be used carefully in an application since it affects the entire port.
Access to a port pin via the FIOxPIN register is conditioned by the corresponding bit of
the FIOxMASK register (see Section 9.5.5
).
FIOxCLR3 Fast GPIO Port x output
Clear register 3. Bit 0 in
FIOxCLR3 register
corresponds to pin Px.24 …
bit 7 to pin Px.31.
8 (byte)
WO
0x00 FIO0CLR3 - 0x2009 C01F
FIO1CLR3 - 0x2009 C03F
FIO2CLR3 - 0x2009 C05F
FIO3CLR3 - 0x2009 C07F
FIO4CLR3 - 0x2009 C09F
FIOxCLRL Fast GPIO Port x output
Clear Lower half-word
register. Bit 0 in FIOxCLRL
register corresponds to pin
Px.0 … bit 15 to pin Px.15.
16 (half-word)
WO
0x0000 FIO0CLRL - 0x2009 C01C
FIO1CLRL - 0x2009 C03C
FIO2CLRL - 0x2009 C05C
FIO3CLRL - 0x2009 C07C
FIO4CLRL - 0x2009 C09C
FIOxCLRU Fast GPIO Port x output
Clear Upper half-word
register. Bit 0 in FIOxCLRU
register corresponds to pin
Px.16 … bit 15 to Px.31.
16 (half-word)
WO
0x0000 FIO0CLRU - 0x2009 C01E
FIO1CLRU - 0x2009 C03E
FIO2CLRU - 0x2009 C05E
FIO3CLRU - 0x2009 C07E
FIO4CLRU - 0x2009 C09E
Table 108. Fast GPIO port output Clear byte and half-word accessible register
description …continued
Generic
Register
name
Description Register
length (bits)
& access
Reset
value
PORTn Register
Address & Name